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CX82100-52 参数 Datasheet PDF下载

CX82100-52图片预览
型号: CX82100-52
PDF下载: 下载PDF文件 查看货源
内容描述: 家庭网络处理器( HNP ) [Home Network Processor (HNP)]
分类和应用:
文件页数/大小: 226 页 / 1406 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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CX82100 Home Network Processor Data Sheet  
8
USB Interface Description  
The USB Interface (or UDC Core) consists of three major functions: USB Controller  
(USBC), APB/DMA Interface (I/F), and USB Differential Transceiver (Figure 8-1). The  
USBC includes the following functions:  
Phase Locked Loop (PLL) Block. The PLL Block extracts the USB clock and data  
from the USB cable. The input to the PLL Block comes from an USB Differential  
Transceiver. The PLL runs on a 48 MHz clock. The PLL also generates a 12 MHz  
clock from the 48 MHz clock and supplies it to the Serial Interface Engine (SIE) and  
USB Bridge Layer (UBL) blocks. The PLL identifies the Single Ended Zero (SE0)  
signal on the USB and sends it to the SIE Block.  
Serial Interface Engine (SIE) Block. The SIE Block performs the front end  
functions of the USB protocol such as SyncField identification, NRZI-NRZ  
conversion, token packet decoding, bit stripping, bit stuffing, NRZ-NRZI  
conversion, CRC5 checking, and CRC16 generation and checking. The SIE also  
converts the serial packet to 8-bit parallel data. The SIE Block has a 1-byte buffer for  
buffering the data during data transmission and reception.  
USB Bridge Layer (UBL) Block. The UBL Block handles the error recovery  
mechanism during transactions while interfacing to the Application (the Application  
includes the APB/DMA I/F, the ARM940T Processor, and the ARM firmware  
processing the data). The UBL also decodes and handles all the Standard Control  
Transfers addressed to Endpoint Zero. The UBL passes some USB commands onto  
the APB/DMA I/F so that the Application can decode and process the command. The  
UBL Block has two sub-blocks called the Protocol Layer (PL) Block and the  
Endpoint (EP) Block.  
The PL Block controls the SIE Block by providing necessary handshake signals to  
the SIE and communicates with the APB/DMA I/F. It also performs error recovery if  
the APB/DMA I/F violates the data transfer protocol.  
The EP Block handles all the Control transfers to Endpoint Zero. The EP Block  
decodes and responds to all the USB Standard Commands and some other USB  
Commands (e.g., Get Descriptor) to the APB/DMA I/F. The EP Block maintains the  
buffer for Device Address, buffer for storing the present active Configuration, and  
the logic to determine the present state of the Device (USBC).  
Endpoint Information (EPINFO) Block: The EPINFO maintains the registers that  
store information about the endpoints. The EPINFO also stores the information about  
the size of Configuration in the USBC. The information about the current endpoint is  
multiplexed from these registers and is provided to the PL Block which controls the  
SIE Block based on this information. The EPINFO also includes the  
DATA0/DATA1 synchronization bits for each bidirectional endpoint the USBC  
supports. Also, the EPINFO includes the EndPtStalled bit for each of the supported  
logical endpoints to indicate the Stalled Status of the Endpoint. The HNP EPINFO  
supports up to 3 active bidirectional logical endpoints and one interrupt endpoint.  
The endpoint number ranges from 0 to 4.  
101306C  
Conexant Proprietary and Confidential Information  
8-1  
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