CX82100 Home Network Processor Data Sheet
7.11.3
EMAC x Network Access Register (E_NA_1: 0x00310004 and E_NA_2:
0x00320004)
E_NA_1 and E_NA_2 are the EMAC Network Access registers for EMAC1 and
EMAC2, respectively.
Bit(s)
31
Type
RW
Default
1’b1
Name
E_NA_RTX
Description
TX Software Reset.
0 = No effect.
1 = Once 1 is written, write 0 into field to get out of reset. All internal
registers of RX and TX (including all bits of this register) are
reset to their default value.
30
RW
RW
1’b0
1’b0
E_NA_STOP
E_NA_HP
Stop Transmit Control.
0 = No effect.
1 = Stop the transmitter after the current frame (if any).
Unused.
Hash/Perfect Address Filter Mode Control.
29:28
27
E_NA_HP, E_NA_HO, E_NA_IF, E_NA_PR, E_NA_PM should be
programmed according to Table 7-7 to select the desired address
filtering mode.
26
25
24
23
22
RW
RW
RW
RW
RW
1’b0
1’b0
1’b0
1’b0
1’b0
E_NA_HO
E_NA_IF
Hash Only Control.
See E_NA_HP for description.
Inverse Filter Control.
See E_NA_HP for description.
Promiscuous Mode Control.
See E_NA_HP for description.
Pass All Multicast.
E_NA_PR
E_NA_PM
E_NA_PB
See E_NA_HP for description.
Pass Bad Packet Control.
0 = Disable.
1 = Receive any packets, if pass address filter, including runt
packets, CRC error, truncated packets.
RX Software Reset.
0 = No effect.
21
RW
1’b1
E_NA_RRX
1 = Once 1 is written, write 0 into field to get out of reset. All internal
RX registers are reset to their default value. This bit can only be
cleared after E_NA_RTX bit is cleared.
20
19
RW
RW
RW
RW
1’b0
1’b0
E_NA_THU
E_NA_DIS
E_NA_RUT
E_NA_IFG
TX Test HUJ Control.
TX Disable Back-Off Counter Control.
TX Reset Unit Timer Control.
Interframe Gap (IFG) Period Select.
18
1’b0
17:16
2’b00
Value is read as an integer and substitutes E_NA_IFG in the following
equations:
100 Mbps: IFG = 960 – 40* E_NA_IFG ns
10 Mbps: IFG = 9600 – 40* E_NA_IFG ns
7-30
Conexant Proprietary and Confidential Information
101306C
CONEXANT [ CONEXANT SYSTEMS, INC ]
