CX28394/28395/28398
2.0 Circuit Description
Quad/x16/Octal—T1/E1/J1 Framers
2.2 Receiver
The Receive Data Link FIFO #1 [RDL1; addr 0A8] is 64 bytes. The Receive
FIFO buffer is formatted differently than the transmit FIFO buffer. The Receive
buffer contains not only received messages, but also a status byte preceding each
message that specifies the size of the received message and the status of that
message. The message status reports if the message was aborted, received with a
correct or incorrect FCS, or continued. A continued message means the byte
count represents a partial message. When all message bytes are read, the buffer
contains another status byte. Message bytes can be differentiated from status
bytes in the buffer by reading the RSTAT1 bit in the RDL #1 Status register
[RDL1_STAT; addr 0A9]. RSTAT1 reports whether the next byte read from the
buffer will be a status byte or some number of message bytes.
The receive data link controller has a versatile microprocessor interface that
can be tuned to the system’s CPU bandwidth. For systems with one dedicated
CPU, the data link status can be polled. For systems where a single CPU controls
multiple devices, the data link can be interrupt-driven. See Figures 2-5 and 2-6
for a high-level description of polling and interrupt driven Receive Data Link
Controller software.
Using the Receive FIFO buffer, an entire block of data can be received with
very little microprocessor interrupt overhead. Block transfers from the buffer can
be controlled by the Near Full Threshold in the FIFO Fill Control register
[RDL1_FFC; addr 0A7]. The Near Full Threshold is a user programmable value
between 0 and 63. This value represents the maximum number of bytes that can
be placed in the Receive buffer without the near full being declared. Once the
threshold is set, the Near Full Status (RNEAR1) in RDL #1 Status [RDL1_STAT;
addr 0A9] is asserted when the Near Full Threshold is reached. An interrupt,
RNEAR, in Data Link 1 Interrupt Status [ISR2; addr 009], is also available to
mark this event.
The device uses a hierarchical interrupt structure, with one top-level interrupt
request register directing software to the lower levels (see Master Interrupt
Request register; addr 081 and Interrupt Request register; addr 003). Of all the
interrupt sources, the two most significant bandwidth requirements are signaling
and data link interrupts. Each data link controller has a top-level interrupt status
register that reports data link operations (see Data Link 1 and 2 Interrupt Status
registers [ISR2, ISR1; addr 009 and 00A). The processor uses a three-step
interrupt scheme for the data link:
1. Read the Master Interrupt Request register to determine which framer
interrupted.
2. Read the Interrupt Request register for that framer.
3. Use that register value to read the corresponding Data Link Interrupt
Status register.
100054E
Conexant
2-17
CONEXANT [ CONEXANT SYSTEMS, INC ]
