CX28394/28395/28398
2.0 Circuit Description
Quad/x16/Octal—T1/E1/J1 Framers
2.2 Receiver
2.2.8 External Receive Data Link (CX28394 and CX28398 Only)
The External Data Link (DL3) provides signal access to any bit(s) in any time slot
of all frames, odd frames, or even frames, including T1 framing bits. Pin access to
the DL3 receiver is provided through RDLCKO and RDLO. These two pins serve
as the DL3 clock output (RDLCKO) and data output (RDLO). The data link mode
of the pins is selected using the RDL_IO bit in the Programmable Input/Output
register [PIO; addr 018].
Control of DL3 is provided in two registers: External Data Link Channel
[DL3_TS; add 015] and External Data Link Bit [DL3_BIT; addr 016]. RDL3 is
set up by selecting the bit(s) (DL3_BIT) and time slot [TS[4:0]; addr 015] to be
monitored, and then enabling the data link [DL3EN; addr 015], which starts the
RDLCKO and TDLCKO gapped clock outputs that mark the selected bits, as
shown in Figure 2-4.
NOTE: DL3 signals are not provided on the CX28395. Therefore, DL3_TS must
be written to 00 to disable the DL3 transmitter and prevent transmit data
corruption.
Figure 2-4. Receive External Data Link Waveforms
Frame 1
2
Frame 2
Frame 3
Frame 4
Frame 5
RDLO
(T1: ESF)
F
1
23 24
F
1
2
23 24
F
1
2
23 24
F
1
2
23 24
F
1
2
23 24
F
1
2
RDLCKO
RCKi
TS24
F
TS1
RDLO
RDLCKO
NOTE(S): This waveform represents ESF FDL extraction; any combination of bits can alternatively be selected.
2.2.9 Sa-Byte Receive Buffers
The Sa-Byte buffers give read access to the odd frame Sa bits in E1 mode. Five
receive Sa-Byte buffers [RSA4 to RSA8; addr 05B to 05F] are available. As a
group, the buffers are updated every multiframe from Sa-bits received in TS0.
This gives the processor up to 2 ms after the receive multiframe interrupt [RMF;
addr 008] occurs to read any Sa-Byte buffer before the buffer content changes.
100054E
Conexant
2-15
CONEXANT [ CONEXANT SYSTEMS, INC ]
