CX28394/28395/28398
2.0 Circuit Description
Quad/x16/Octal—T1/E1/J1 Framers
2.2 Receiver
2.2.2 In-Band Loopback Code Detection
The in-band loopback code detector circuitry detects receive data with in-band
codes of configurable value and length. These codes can be used to request
loopback of terminal equipment signals or other user specified applications. The
two codes are referred to as loopback-activate and loopback-deactivate, although
the detectors need not be used only for loopback codes. Generally, any repeating
1–7 bit pattern can be selected. The loopback application is described in Section
9.3.1 of ANSI T1.403-1995. The loopback activate code is set in the Loopback
Activate Code Pattern [LBA; addr 043]. The loopback deactivate code is set in the
Loopback Deactivate Code Pattern [LBD; addr 044].
The sequence length for the loopback activate and deactivate codes can be
programmed for 4, 5, 6, or 7 bits by setting the code length bits of the Receive
Loopback Code Detector Configuration register [RLB; addr 042]. Shorter codes
can be programmed by repeating the expected pattern (e.g. 3+3 bit code
programmed as 6-bit code).
T1 In-Band Loopback Codes
Activate 00001
Deactivate 001
When a loopback code is detected, the LOOPUP or LOOPDN status bit is set
in Alarm 2 register [ALM2; addr 048], and the corresponding LOOPUP or
LOOPDN bit in Alarm 2 Interrupt Status register (ISR6; addr 005] is set. The
loopback detection interrupt can be enabled using the Alarm 2 Interrupt Enable
register [IER6; addr 00D]. When enabled, a loop-up or loop-down code detection
causes the Alarm 2 Interrupt bit [ALARM2] to be set in the Interrupt Request
register [IRR; addr 003] and generates an interrupt. Since loopbacks are not
automatically initiated, the processor must intercept and interpret the interrupt
status condition to determine when it must enable or disable the loopback control
mechanism (e.g., LLOOP; addr 014).
2.2.3 Error Counters
The following Performance Monitoring (PM) counters are available in the RCVR:
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•
•
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Framing Bit Errors (FERR)
CRC Errors (CERR)
Line Code Violations (LCV)
Far End Block Errors (FEBE)
All PM count registers are reset on read unless LATCH_CNT is set in the
Alarm/Error/Counter Latch Configuration register [LATCH; addr 046].
LATCH_CNT enables the one-second latching of counts coincident with the
one-second timer interrupt [ISR6; addr 005]. One-second latching of PM counts
is required if AUTO_PRM responses are enabled. All PM counters can be
disabled during RLOF, RLOS, and RAIS, using the STOP_CNT bit in the
LATCH register.
Note that if STOP_CNT is negated, error monitoring during RLOF conditions
will detect FERR, CERR, and FEBE according to the last known frame
alignment.
100054E
Conexant
2-5
CONEXANT [ CONEXANT SYSTEMS, INC ]
