CX28394/28395/28398
2.0 Circuit Description
Quad/x16/Octal—T1/E1/J1 Framers
2.1 Functional Block Diagram
Figure 2-2. Detailed Framer Block Diagram (Non-multiplexed System Bus Mode)
MCLK
RDLO[1] RDLCKO[1]
(1)
(1)
RSIG
Stack
MOTO*
RSIG
Buffer
External DLINK
PRBS/Inband LB
DLINK2 Buffer
DLINK1 Buffer
Sa-Byte/BOP
PDV Monitor
SYNCMD
RSIGO[1]
RSIG
Local
SYSCKI
RNRZI[1]
CS*
AS*
DS*
RPCMO[1]
(1)
(1)
RSLIP
Buffer
RPOSI[1]
RNEGI[1]
RZCS
Decoder
AIS
SIGFRZ[1]
RINDO[1]
Error Counters
Alarm Monitor
Receiver Framer
R/W*
DTACK*
AD[7:0]
RSB
Timebase
RFSYNC[1]
RPHASE
Receive
Timebase
RMSYNC[1]
RSBCKI[1]
RCKI[1]
TCKO[1]
A[11:0]
INTR*
TCKI[1]
E1ACKI
TIACKI
ONESEC
RST*
Clock
TSBCKI[1]
Monitor
TFSYNC[1]
TSB
Transmitter
Timebase
TPHASE
TMSYNC[1]
TINDO[1]
Timebase
(1)
SERCS[1:0]
Transmit
Framer
SERCLK
SERDO
SERI
TSLIP
Buffer
(1)
TPOSO[1]
TNEGO[1]
TPCMI[1]
TSIGI[1]
TZCS
Encoder
(1)
TSIG
TNRZO[1]
TCK
TMS
TDI
Buffer
MSYNCO [1]
(1)
TDLI[1]
TSIG
Buffer
(1)
TDLCKO[1]
TDO
FRAMER 1
TRST*
FRAMER N
NOTE(S):
(1)
Not available on CX28395.
100054E
Conexant
2-3
CONEXANT [ CONEXANT SYSTEMS, INC ]
