CX28394/28395/28398
2.0 Circuit Description
Quad/x16/Octal—T1/E1/J1 Framers
2.2 Receiver
2.2.5.6 Multiframe YEL
The criteria for Multiframe Yellow Alarm is described in Table 3-13, Receive
Yellow Alarm Set/Clear Criteria. The MYEL real-time status is available in
ALM1, and the interrupt is available in ISR7.
2.2.5.7 Severely Errored
Frame
A SEF is reported when the receive signal does not meet the requirements of
ANSI T1.231. SEF real-time status is available in ALM3. A 2-bit counter is also
available [SEF; addr 05A]. An interrupt is available in ISR4 to indicate that the
SEF counter overflowed.
2.2.5.8 Change of
Frame
Each COFA increments a 2-bit counter [COFA; addr 05A]. An interrupt is
available in ISR4 to indicate that the COFA counter overflowed.
Alignment
2.2.5.9 Receive
Multiframe AIS
Receive Multiframe AIS (RMAIS) is reported when the receive TS16 signal
contains three or fewer zeros out of 128 bits in each multiframe over two
consecutive multiframes, according to the requirements of ITU–T
Recommendation G.775. RMAIS is only checked in E1 CAS mode. RMAIS
real-time status is available in ALM3 [addr 049].
2.2.6 Test Pattern Receiver
The test pattern receiver circuitry can sync on framed or unframed PRBS patterns
and count bit errors. This feature is particularly useful for system diagnostics,
production testing, and test equipment applications. The PRBS patterns available
include 2E11-1, 2E15-1, 2E20-1, and 2E23-1. Each pattern can optionally include
Zero Code Suppression (ZCS).
The Receive Test Pattern Configuration register [RPATT; addr 041] controls
the test pattern receiver circuit. The BSTART control bit (in RPATT) must be
active to enable the test pattern receiver and to begin counting bit errors. RPATT
controls the PRBS pattern, ZCS setting (ZLIMIT), and T1/E1 framing
(FRAMED). RPATT selects which PRBS pattern the receiver should hunt for
pattern sync. ZLIMIT selects the maximum number of consecutive zeros the
pattern is allowed to contain. FRAMED mode informs the PRBS pattern receiver
not to search for the pattern in the frame bit in T1 mode or search for the pattern
in time slot 0 (and time slot 16 if CAS framing is selected) in E1 mode. CAS
framing is selected by setting RFRAME[3] to 1 in the Primary Control register
[CR0; addr 001]. If FRAMED is disabled, the PRBS pattern receiver searches all
time slots for the test pattern.
The RESEED bit in RPATT informs the receive PRBS sync circuit to begin a
PRBS pattern search. Once the search begins, any additional writes to RESEED
restarts the pattern sync search at a different point in the pattern. The time to sync
depends on the pattern and number of bit errors in the pattern.
Pattern sync is reported (when found) in PSYNC status of the Pattern
Interrupt Status register [ISR0; addr 00B]. Next, the PRBS Pattern Error counter
[BERR; addr 058 and 059] counts bit errors detected on the incoming pattern,
provided that BSTART remains active. Error counting stops if the BSTART bit is
cleared. The BERR counter is reset to zero after every read, or latched on every
ONESEC interrupt as selected by LATCH_CNT [addr 046]. An interrupt is
available to indicate the BERR counter overflowed in ISR4.
100054E
Conexant
2-9
CONEXANT [ CONEXANT SYSTEMS, INC ]
