4.0 Electrical/Mechanical Specifications
CX28394/28395/28398
4.5 MPU Interface Timing
Quad/x16/Octal—T1/E1/J1 Framers
Figure 4-11. Intel Synchronous Read Cycle
MOTO* = 1, SYNCMD = 1
MCLK
1
ALE
2
9
A[8]
AD[7:0]
RD*
Address
3
7
Address
Read Data
8
4
5
6
WR*
CS*
Table 4-14. Intel Synchronous Read Cycle
Symbol
Parameter
ALE high pulse width
Minimum
Maximum
Units
1
2
3
4
5
6
7
8
9
15
2
—
—
—
—
—
—
(1)
25
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
A[8], AD[7:0] Address setup to ALE low
A[8], AD[7:0] Address hold after ALE low
ALE low to RD* and CS* both low
5
5
RD*, CS*, WR* setup to MCLK high (Start RD cycle)
RD*, CS*, WR* hold after MCLK high
Start RD* cycle to AD[7:0] valid
3
5
—
0
RD* or CS* high to AD[7:0] invalid/three-state
End RD cycle to next ALE high
0
NOTE(S):
(1)
Parameter 7 equals 40 ns or 1/2* MCLK + 17 ns, whichever is greater.
4-14
Conexant
100054E
CONEXANT [ CONEXANT SYSTEMS, INC ]
