CX28394/28395/28398
4.0 Electrical/Mechanical Specifications
Quad/x16/Octal—T1/E1/J1 Framers
4.5 MPU Interface Timing
Figure 4-12. Intel Synchronous Write Cycle
MOTO* = 1, SYNCMD = 1
MCLK
1
8
ALE
2
A[8]
AD[7:0]
WR*
Address
3
6
Address
Write Data
7
RD*
4
5
CS*
Table 4-15. Intel Synchronous Write Cycle
Symbol
Parameter
ALE high pulse width
Minimum
Maximum
Units
1
2
3
4
5
6
7
8
15
—
ns
ns
ns
ns
ns
ns
ns
ns
A[8], AD[7:0] Address setup to ALE low
A[8], AD[7:0] Address hold after ALE low
2
—
5
—
WR*,RD*,CS* setup to MCLK high (start WR cycle)
WR*,RD*,CS* hold after MCLK high
2
5
—
—
1/MCLK–10
—
Start WR* cycle to AD[7:0] input data valid
AD[7:0] input data hold after Start WR cycle
Start WR cycle to next ALE high
—
1/MCLK+9
1/MCLK+10
—
100054E
Conexant
4-15
CONEXANT [ CONEXANT SYSTEMS, INC ]
