4.0 Electrical/Mechanical Specifications
CX28394/28395/28398
4.5 MPU Interface Timing
Quad/x16/Octal—T1/E1/J1 Framers
Figure 4-7. Intel Asynchronous Read Cycle
MOTO* = 1, SYNCMD = 0
1
ALE
2
9
A[8]
AD[7:0]
RD*
Address
3
Address
Read Data
7
4
6
WR*
5
8
CS*
Table 4-10. Intel Asynchronous Read Cycle
Symbol
Parameter
ALE high pulse width
Minimum
Maximum
Units
1
2
3
4
5
6
7
8
9
15
2
—
—
—
—
—
80
25
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
A[8], AD[7:0] Address setup to ALE low
A[8], AD[7:0] Address hold after ALE low
ALE low to RD* and CS* both low
5
0
WR* high setup to RD* and CS* both low
RD* and CS* both low to AD[7:0] valid
0
—
0
RD* or CS* high to AD[7:0] invalid/three-state
WR* high hold after RD* or CS* high
RD* or CS* high to next ALE
0
0
4-10
Conexant
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