Table 3-35. Transmitter Registers
Bit Number
ADDR
(hex)
Register
Label
Read
Write
7
6
5
4
3
2
1
0
070
071
072
073
074
075
076
077
078
TCR0
TCR1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
TNRZ
—
—
TABORT
—
—
TFORCE
INS_MYEL
TBERR
INS_SA[6]
AUTO_MYEL
—
—
TFRAME[3]
TLOFB
TFRAME[2]
TLOFA
TFRAME[1]
TZCS[1]
INS_CRC
TFERR
TFRAME[0]
TZCS[0]
INS_FBIT
TVERR
TFEBE
TLOFC
TFRM
TERROR
TMAN
TALM
TPATT
TLB
INS_YEL
BSLIP
INS_MF
TCOFA
INS_FE
TCERR
TSERR
INS_SA[8]
—
TMERR
INS_SA[7]
AISCLK
—
INS_SA[5]
AUTO_YEL
TPSTART
—
INS_SA[4]
AUTO_AIS
FRAMED
LB_LEN[1]
LBP[5]
FEBE_II
TMYEL
FEBE_I
TYEL
TAIS
—
ZLIMIT
TPATT[1]
UNFRAMED
LBP[7]
TPATT[0]
LBSTART
—
—
—
—
LB_LEN[0]
LBP[6]
LBP
LBP[1]
LBP[2]
LBP[3]
LBP[4]
Table 3-36. Transmit Sa-Byte Buffers
Bit Number
ADDR
(hex)
Register
Label
Read
Write
7
6
5
4
3
2
1
0
07B
07C
07D
07E
07F
TSA4
TSA5
TSA6
TSA7
TSA8
R/W
R/W
R/W
R/W
R/W
TSA4[7]
TSA5[7]
TSA6[7]
TSA7[7]
TSA8[7]
TSA4[6]
TSA5[6]
TSA6[6]
TSA7[6]
TSA8[6]
TSA4[5]
TSA5[5]
TSA6[5]
TSA7[5]
TSA8[5]
TSA4[4]
TSA5[4]
TSA6[4]
TSA7[4]
TSA8[4]
TSA4[3]
TSA5[3]
TSA6[3]
TSA7[3]
TSA8[3]
TSA4[2]
TSA5[2]
TSA6[2]
TSA7[2]
TSA8[2]
TSA4[1]
TSA5[1]
TSA6[1]
TSA7[1]
TSA8[1]
TSA4[0]
TSA5[0]
TSA6[0]
TSA7[0]
TSA8[0]