Table 3-39. System Bus Registers (2 of 2)
Bit Number
ADDR
(hex)
Register
Label
Read
Write
7
6
5
4
3
2
1
0
0D8
0D9
RSYNC_FRM
SSTAT
R/W
R
—
TSDIR
—
—
TUSLIP
—
OFFSET[14]
TDLY
OFFSET[13]
RSDIR
OFFSET[12]
RFSLIP
OFFSET[11]
RUSLIP
OFFSET[10]
RDLY
TFSLIP
MORE
WORD
CH[4]
CH[3]
CH[2]
CH[1]
CH[0]
0DA
STACK
R
WORD
MORE
—
—
SIG_BITA
RDELAY[1]
TDELAY[1]
—
SIG_BITB
RDELAY[0]
TDELAY[0]
PERR_TPC
TINDO
SIG_BITC
RSLIP_WR
TSLIP_WR
PERR_RPC
TSIG_AB
TSIGC
SIG_BITD
RSLIP_RD
TSLIP_RD
PERR_SBC
ASSIGN
TSIGD
0DB
0DC
RPHASE
TPHASE
R
RDELAY[5]
TDELAY[5]
—
RDELAY[4]
TDELAY[4]
—
RDELAY[3]
TDELAY[3]
—
RDELAY[2]
TDELAY[2]
—
R
0DD
PERR
R
0E0–0FF
100–11F
120–13F
SBCn; n = 0 to 31
TPCn; n = 0 to 31
TSIGn; n = 00 to 31
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
INSERT
TLOOP
—
SIG_LP
TIDLE
RLOOP
TLOCAL
—
RINDO
TB7ZS/EMFBIT
—
TSIGA/TSIGO
TSIGn[3]
TPCM[5]
TPCM[5]
RSIGA
TSIGB/RSIGO
TSIGn[2]
TPCM[6]
TPCM[6]
RSIGB
—
TSIGn[1]
TPCM[7]
TPCM[7]
RSIGC
TSIGn[0]
TPCM[8]
TPCM[8]
RSIGD
140–15F TSLIP_LOn; n = 0 to 31
160–17F TSLIP–HIn; n = 0 to 31
TPCM[1]
TPCM[1]
RSIG_AB/ EMFBIT
RSIGn[7]
RPCM[1]
RPCM[1]
TPCM[2]
TPCM[2]
RIDLE
TPCM[3]
TPCM[3]
SIG_STK
RSIGn[5]
RPCM[3]
RPCM[3]
TPCM[4]
TPCM[4]
RLOCAL
RSIGn[4]
RPCM[4]
RPCM[4]
180–19F
1A0–1BF
RPCn; n = 0 to 31
RSIGn; n = 0 to 31
RSIGn[6]
RPCM[2]
RPCM[2]
RSIGn[3]
RPCM[5]
RPCM[5]
RSIGn[2]
RPCM[6]
RPCM[6]
RSIGn[1]
RPCM[7]
RPCM[7]
RSIGn[0]
RPCM[8]
RPCM[8]
1C0–1DF RSLIP_LOn; n = 0 to 31
1E0–1FF RSLIP_HIn; n = 0 to 31
CONEXANT [ CONEXANT SYSTEMS, INC ]
