Table 3-38. Data Link Registers (2 of 2)
Bit Number
ADDR
(hex)
Register
Label
Read
Write
7
6
5
4
3
2
1
0
EOM[1]
RDL2[7]
—
EOM[0]
RDL2_CNT[5]
RDL2[5]
—
RDL2_CNT[4]
RDL2[4]
RMSG2
RDL2_CNT[3]
RDL2[3]
RDL2_CNT[2]
RDL2[2]
RDL2_CNT[1]
RDL2[1]
RDL2_CNT[0]
RDL2[0]
0B3
RDL2
R
RDL2[6]
0B4
0B6
0B7
0B8
0B9
0BA
0BB
0BC
0BD
0BE
RDL2_STAT
TDL2_FEC
TDL2_EOM
TDL2
R
—
RSTAT2
RMPTY2
RNEAR2
RFULL2
R/W
W
—
—
FEC[5]
FEC[4]
FEC[3]
FEC[2]
FEC[1]
FEC[0]
—
—
—
—
—
—
—
—
R/W
R
TDL2[7]
—
TDL2[6]
TDL2[5]
—
TDL2[4]
—
TDL2[3]
TDL2[2]
TDL2[1]
TDL2[0]
TDL2_STAT
DL_TEST1
DL_TEST2
DL_TEST3
DL_TEST4
DL_TEST5
—
TMSG2
TMPTY2
TNEAR2
TFULL2
R/W
R/W
R/W
R/W
R/W
—
—
—
—
—
DL_TEST1[3]
DL_TEST2[3]
DL_TEST3[3]
DL_TEST4[3]
DL_TEST5[3]
DL_TEST1[2]
DL_TEST2[2]
DL_TEST3[2]
DL_TEST4[2]
DL_TEST5[2]
DL_TEST1[1]
DL_TEST2[1]
DL_TEST3[1]
DL_TEST4[1]
DL_TEST5[1]
DL_TEST1[0]
DL_TEST2[0]
DL_TEST3[0]
DL_TEST4[0]
DL_TEST5[0]
—
DL_TEST2[5]
DL_TEST3[5]
DL_TEST4[5]
DL_TEST5[5]
DL_TEST2[4]
DL_TEST3[4]
DL_TEST4[4]
DL_TEST5[4]
—
—
—
DL_TEST4[6]
DL_TEST5[6]
—
Table 3-39. System Bus Registers (1 of 2)
Bit Number
ADDR
(hex)
Register
Label
Read
Write
7
6
5
4
3
2
1
0
0D0
0D1
0D2
0D3
0D4
0D5
0D6
0D7
SBI_CR
RSB_CR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
X2CLK
SBI_OE
SIG_OFF
—
EMF
RPCM_NEG
—
EMBED
RSYN_NEG
—
SBI[3]
BUS_FRZ
—
SBI[2]
SBI[1]
RSBI[1]
SBI[0]
RSBI[0]
BUS_RSB
RSB_CTR
OFFSET[2]
OFFSET[5]
TSB_CTR
OFFSET[2]
OFFSET[5]
FRZ_OFF
RSYNC_BIT
RSYNC_TS
TSB_CR
—
OFFSET[1]
OFFSET[4]
TSBI[1]
OFFSET[0]
OFFSET[3]
TSBI[0]
—
BUS_TSB
—
OFFSET[9]
TX_ALIGN
—
OFFSET[8]
TPCM_NEG
—
OFFSET[7]
TSYN_NEG
—
OFFSET[6]
TSB_ALIGN
—
TSYNC_BIT
TSYNC_TS
RSIG_CR
OFFSET[1]
OFFSET[4]
FRZ_ON
OFFSET[0]
OFFSET[3]
THRU
—
OFFSET[9]
SET_RSIG
OFFSET[8]
SET_SIG
OFFSET[7]
UNICODE
OFFSET[6]
DEBOUNCE
—
CONEXANT [ CONEXANT SYSTEMS, INC ]
