3.0 Registers
CX28394/28395/28398
3.11 Receive Sa-Byte Buffers
Quad/x16/Octal—T1/E1/J1 Framers
3.11 Receive Sa-Byte Buffers
Five receive Sa-Byte buffers [RSA4–RSA8] are double-buffered. All five registers are updated with the Sa-bits
received in TS0 of odd frames at each receive multiframe interrupt [RMF; addr 008]. Bit 0 of all RSA registers
contains data from frame 1, Bit 1 contains data from frame 3, Bit 2 contains data from frame 5, etc. This gives
the processor a full 2 ms after RMF interrupt to read any Sa-Byte buffer before the buffer content changes.
Processor should ignore RSA buffer contents at all times during T1 mode and also when receiver reports loss of
FAS alignment [FRED=1; addr 049] in E1 mode.
05B—Receive Sa4 Byte Buffer (RSA4)
7
6
5
4
3
2
1
0
RSA4[7]
RSA4[6]
RSA4[5]
RSA4[4]
RSA4[3]
RSA4[2]
RSA4[1]
RSA4[0]
RSA4[7]
Sa4 bit received in frame 15
Sa4 bit received in frame 13
Sa4 bit received in frame 11
Sa4 bit received in frame 9
Sa4 bit received in frame 7
Sa4 bit received in frame 5
Sa4 bit received in frame 3
Sa4 bit received in frame 1
RSA4[6]
RSA4[5]
RSA4[4]
RSA4[3]
RSA4[2]
RSA4[1]
RSA4[0]
05C—Receive Sa5 Byte Buffer (RSA5)
7
6
5
4
3
2
1
0
RSA5[7]
RSA5[6]
RSA5[5]
RSA5[4]
RSA5[3]
RSA5[2]
RSA5[1]
RSA5[0]
RSA5[7]
Sa5 bit received in frame 15
Sa5 bit received in frame 13
Sa5 bit received in frame 11
Sa5 bit received in frame 9
Sa5 bit received in frame 7
Sa5 bit received in frame 5
Sa5 bit received in frame 3
Sa5 bit received in frame 1
RSA5[6]
RSA5[5]
RSA5[4]
RSA5[3]
RSA5[2]
RSA5[1]
RSA5[0]
3-52
Conexant
100054E
CONEXANT [ CONEXANT SYSTEMS, INC ]
