3.0 Registers
CX28394/28395/28398
3.7 Primary Control and Status Registers
Quad/x16/Octal—T1/E1/J1 Framers
01A—Clock Input Mux (CMUX)
Unused bits are reserved and should be written to 0.
7
6
5
4
3
2
1
0
—
RSBCK
—
TSBCK
—
—
TXCLK[1]
TXCLK[0]
RSBCK
TSBCK
RSBCK Source Select—Internal clock mux selects from one of two clock signals for
application to the RSB timebase. The RSBCKI input pin is ignored if TSBCKI is selected.
RSBCK
RSBCK Source
RSBCKI pin
TSBCKI pin
Notes
Normal RSB timebase
RSB slaved to TSB
0
1
TSBCK Source Select—Internal clock mux selects from one of three clock signals for
application to the TSB timebase. If TSLIP is bypassed [TSB_CR; addr 0D4], TCKI is selected.
The TSBCKI input pin is ignored if TCKI or RSBCKI is selected.
TSBCK
TSBCK Source
TSBCKI pin
RSBCKI pin
TCKI pin
Notes
Normal TSB timebase
0
1
x
TSB slaved to RSB
TSLIP is bypassed
TXCLK[1:0]
TXCLK Source Select—Internal transmit clock mux selects from one of three clock signals.
The selected clock signal is applied to transmit clock monitor, acts as a timing reference for the
transmitter block, and must operate at the T1/E1 line rate. The selected clock signal also
appears on TCKO pin. The TCKI input pin is ignored whenever a clock source other than
TCKI is selected.
TXCLK[1:0]
TXCLK Source
TCKI
Notes
00
01
10
Normal transmit (With TSLIP)
Transmit slaved to receiver (Loop Timed)
Transmit slaved to RSB
RCKI
RSBCKI
020—Receive Alarm Configuration (RAC)
Unused bits are reserved and should be written to 0.
7
6
5
4
3
2
1
0
—
—
—
RAL_CON
—
—
—
—
RAL_CON
RALOS Alarm Configuration – Determines whether RALOS [ALM1; addr 047] reports loss
of receive clock (RCKI) or loss of receive signal for 1 msec.
0 = RALOS reports that RLOS [ALM1; addr 047] has been active for 1 msec
1 = RALOS reports loss of clock on RCKI pin
3-34
Conexant
100054E
CONEXANT [ CONEXANT SYSTEMS, INC ]
