CX28394/28395/28398
3.0 Registers
Quad/x16/Octal—T1/E1/J1 Framers
3.7 Primary Control and Status Registers
018—Programmable Input/Output (PIO)
7
6
5
4
3
2
1
0
RMSYNC_EN
RDL_IO
TMSYNC_EN
TDL_IO
RFSYNC_IO
RMSYNC_IO
TFSYNC_IO
TMSYNC_IO
RMSYNC_EN
RDL_IO
Enable RMSYNC—Select which signal is present on bimodal pin, RFSYNC/RMSYNC.
When active, receiver multiframe sync (RMSYNC) is enabled. Otherwise, receiver frame sync
RFSYNC is enabled.
Enable Receiver Data Link—Select which signals are present on bimodal RDLCKO and
RDLO. When active Receiver Data Link Clock Out (RDLCKO) and Receive Data Link Data
Out (RDLO) are enabled. Otherwise RINDO and RSIGO are as follows:
0 = select RINDO and RSIGO
1 = select Receive Data Link
TMSYNC_EN
TDL_IO
Enable TMSYNC—Select which signal is present on bimodal pin, TFSYNC/TMSYNC. When
active, transmit multiframe sync (TMSYNC) is enabled. Otherwise, receiver frame sync
TFSYNC is enabled.
Enable Transmit Data Link—Select which signals are present on bimodal TDLCKO and
TDLI. When active Transmit Data Link Clock Out (TDLCKO) and Transmit Data Link Data
Out (TDLO) are enabled. On the CX28395 device, TDL3 is not available and TDL_IO must be
written to 0.
0 = select TINDO and TSIGI
1 = select Transmit Data Link
RFSYNC_IO
Bidirectional RFSYNC Input/Output Mode—Refer to the system bus sync mode summary in
Tables 3-9 and 3-11. When RFSYNC is an input, its low to high transition aligns the RSB
timebase to the programmed RSB.OFFSET. Refer to RSYNC_BIT, RSYNC_TS, and
RSYNC_FRM offset registers [addr 0D2, 0D3, and 0D8] for a complete description of the
RSB Sync Bits Time Slot and Frame Offset. Once aligned, the RSB timebase internally
flywheels at a 125 µs interval (8 kHz) until a new RFSYNC pulse is applied. When RFSYNC
is programmed as an output, it operates continuously at a 8 kHz frame rate, marking the RSB
sync bits and time slot offset position of each frame. Initial RFSYNC alignment and
subsequent realignment depends upon RSB Mode [RSBI; addr 0D1] and RSB manual center
[RSB_CTR; addr 0D1]. RFSYNC must be programmed as an output when RSLIP is in bypass
mode. RFSYNC and RMSYNC are supplied either by the RSB timebase (output) or receive
system bus (input) at a programmable RSB sync bit offset, time slot location and frame offset
location.
0 = RFSYNC input
1 = RFSYNC output
RMSYNC_IO
Bidirectional RMSYNC Input/Output Mode—Refer to the system bus sync mode summary in
Table 3-9. When RMSYNC is an input, its low-to-high transition aligns the RSB timebase to
the programmed RSB.OFFSET. Once aligned, the RSB timebase internally flywheels at a 3 ms
(T1) or 2 ms (E1) interval until a new RMSYNC pulse is applied. Note that RMSYNC input
signal must always coincide with RFSYNC. When RMSYNC is an output, it operates
continuously at the 6 ms multiframe rate, marking the RSB.OFFSET position of every second
multiframe (T1) or every third multiframe (E1). Initial RMSYNC alignment and subsequent
realignment depends upon RSB mode [RSBI; addr 0D1] and RSB manual center [RSB_CTR;
addr 0D1]. RMSYNC must be programmed as an output when RSLIP is in bypass mode or
transparent signaling mode [THRU; addr 0D7].
0 = RMSYNC input
1 = RMSYNC output
100054E
Conexant
3-31
CONEXANT [ CONEXANT SYSTEMS, INC ]
