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CX28395-19 参数 Datasheet PDF下载

CX28395-19图片预览
型号: CX28395-19
PDF下载: 下载PDF文件 查看货源
内容描述: 四核/ X16 /八路T1 / E1 / J1成帧器 [Quad/x16/Octal?T1/E1/J1 Framers]
分类和应用: 电信集成电路
文件页数/大小: 305 页 / 1863 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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3.0 Registers  
CX28394/28395/28398  
3.7 Primary Control and Status Registers  
Quad/x16/OctalT1/E1/J1 Framers  
015—External Data Link Time Slot (DL3_TS)  
DL3_TS works in conjunction with the DL3_BIT Register [addr 016] to determine which transmit time slots are  
supplied from the TDLI pins and which receive and transmit time slots are accompanied by a gated RDLCKO  
and TDLCKO output. Refer to Figure 2-21, Transmit External Data Link Waveforms. Note that RDLO outputs  
the entire receive data bit stream, and only selective time slots are marked by RDLCKO. DL3 is not accessible  
on the CX28395 device, therefore, DL3_TS must be written to 00.  
CX28394, CX28398  
7
6
5
4
3
2
1
0
DL3EN  
ODD  
EVEN  
TS[4]  
TS[3]  
TS[2]  
TS[1]  
TS[0]  
CX28395  
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
DL3EN  
Enable External Data Link—Active high enables data insertion from TDLI and clock gating  
on TDLCKO and RDLCKO outputs according to the selected external data link mode. PIO  
[addr 018] must select TDL_IO and/or RDL_IO to enable external data link signals.  
0 = external data link pins inactive  
1 = TDLI/TDLCKO and RDLO/RDLCKO active  
ODD/EVEN  
Odd/Even Frame Select—The external data link is programmed to source and sink data bits  
during all frames or odd or even frames only. ODD/EVEN also controls gating of RDLCKO  
and TDLCKO external data link clocks. Frames are counted from 0 through 15 in E1 mode and  
1 through 24 in T1 mode, where frames 1, 3, 5 etc., are always considered ODD frames.  
ODD/EVEN is ignored if T1 Fbits are selected in DL3_TS.  
ODD  
EVEN  
Frame Select  
None. Equivalent to disabling external data link.  
Even frames only. Frame 0, 2, 4, 6, etc.  
Odd frames only. Frame 1, 3, 5, 7, etc.  
All frames  
0
0
1
1
0
1
0
1
TS[4:0]  
External Data Link Time Slot Select—Picks one 8-bit time slot for input and output over the  
external data link pins. Any time slot can be chosen from TS0 to TS31 in E1 mode, or TS1 to  
TS24 in T1 mode. In T1 mode, TS0 selects Fbits instead of a channel time slot.  
00000  
00001  
|
T1 Fbits or E1 Time Slot 0  
Time Slot 1  
|
11110  
11111  
Time Slot 30  
Time Slot 31  
3-28  
Conexant  
100054E  
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