CX28394/28395/28398
3.0 Registers
Quad/x16/Octal—T1/E1/J1 Framers
3.6 Interrupt Enable Registers
3.6 Interrupt Enable Registers
Writing a one to an IER bit allows that specific interrupt source to activate its respective ISR bit, the associated
MIR bit. While cleared, each IER bit allows that source to activate its respective ISR bit, but prevents activation
of the MIR bit.
00C—Alarm 1 Interrupt Enable Register (IER7)
7
6
5
4
3
2
1
0
RMYEL
RYEL
RPDV
RAIS
RALOS
RLOS
RLOF
SIGFRZ
RMYEL
Enable RMYEL Interrupt
Enable RYEL Interrupt
Enable RPDV Interrupt
Enable RAIS Interrupt
Enable RALOS Interrupt
Enable RLOS Interrupt
Enable RLOF Interrupt
Enable SIGFRZ Interrupt
RYEL
RPDV
RAIS
RALOS
RLOS
RLOF
SIGFRZ
00D—Alarm 2 Interrupt Enable Register (IER6)
Unused bits are reserved and should be written to 0.
7
6
5
4
3
2
1
0
LOOPDN
LOOPUP
TPDV
—
TLOC
—
TLOF
ONESEC
LOOPDN
Enable LOOPDN Interrupt
Enable LOOPUP Interrupt
Enable TPDV Interrupt
Enable TLOC Interrupt
Enable TLOF Interrupt
Enable ONESEC Interrupt
LOOPUP
TPDV
TLOC
TLOF
ONESEC
100054E
Conexant
3-23
CONEXANT [ CONEXANT SYSTEMS, INC ]
