1.0 Functional Description
CX25870/871
1.3 Device Description
Flicker-Free Video Encoder with Ultrascale Technology
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SLAVER bit = 1 so the CX25870/871 is the video timing slave. It expects
to receive the syncs from the graphics controller.
EN_BLANKO is high(=1), signifying the CX25870/871's BLANK* port
is an output or that NO BLANK* signal is used as part of the system.
EN_DOT = 0 telling the CX25870/871 to use its internal counters to
determine the active versus the blanking regions.
EN_OUT = 1 ensures there is a clock output (CLKO) from the
CX25870/871.
Table 1-10. Pseudo-Master Interface with a BLANK* Input to the CX25870/871
SLAVER (Bit 5 of
0xBA) ORed with
Slave Pin
EN_BLANKO (MSb
of Register 0xC6)
EN_DOT (Bit 6 of
Register 0xC6)
EN_OUT (LSb of
Register 0xC4)
Interfaced Used
PSEUDO MASTER
BLANK* SIGNAL
transmitted to the
CX25870/871 and
received as an input.
1
0
1
1
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SLAVER bit = 1 so the CX25870/871 is the video timing slave. It expects
to receive the syncs from the graphics controller.
EN_BLANKO is low (= 0), signifying the CX25870/871's BLANK* port
is an input.
EN_DOT = 1 telling the CX25870/871 to use the BLANK* signal it is
receiving to determine where active video starts (rising edge of BLANK*)
and where the blanking region starts (falling edge).
EN_OUT = 1 ensures there is a clock output (CLKO) from the
CX25870/871.
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Table 1-11. Slave Interface without a BLANK* Signal
SLAVER (Bit 5
of 0xBA) ORed
with Slave Pin
EN_BLANKO
(MSb of
Register 0xC6)
EN_DOT (Bit 6
of Register
0xC6)
EN_XCLK (MSb
of Register
0xA0)
EN_OUT (LSb of
Register 0xC4)
Interfaced Used
SLAVE
1
1
0
0
1
BLANK* is NOT
included as part
of the interface.
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After an autoconfiguration command, the CX25870/871 expects active
low VSYNC* and HSYNC* signals from the controller. The format of
pixels at input of encoder needs to be 24-bit RGB multiplexed unless
modifications are made to the IN_MODE[3:0] 4-bit sequence.
In addition to Table 1-11, another bit must be programmed manually with
this interface. The most significant bit of CX25870/871 register 0xA0
must be set. This guarantees that EN_XCLK is high (=1) which will allow
the CX25870/871 to accept CLKI as the pixel clock source.
1-24
Conexant
100381B
CONEXANT [ CONEXANT SYSTEMS, INC ]
