CX25870/871
1.0 Functional Description
Flicker-Free Video Encoder with Ultrascale Technology
1.3 Device Description
•
If the SLAVE pin is tied to GND, the state of the SLAVER bit dictates
whether the CX25870/871 is the timing master or timing slave by
controlling the direction of the HSYNC* and VSYNC* ports. In other
words, SLAVER will determine whether the overall interface is master or
pseudo-master. The SLAVER bit allows the graphics controller vendor to
switch between master video timing and slave video timing through
software so long as the SLAVE pin (#51) is low.
•
•
•
EN_BLANKO is high (=1), signifying the CX25870/871's BLANK* port
is an output or that NO BLANK* signal is used as part of the system.
EN_DOT = 0 telling the CX25870/871 to use its internal counters to
determine the active versus the blanking regions.
EN_OUT = 1 ensures there is a clock output (CLKO) from the
CX25870/871 and also enables HSYNC* and VSYNC* outputs.
Table 1-8. Master Interface with a BLANK* Input to the CX25870/871
SLAVER (Bit 5 of
EN_BLANKO (MSb
EN_DOT (Bit 6 of
Register 0xC6)
EN_OUT (LSb of
Register 0xC4)
Interfaced Used
0xBA) ORed with
Slave Pin
of Register 0xC6)
MASTER
0
0
1
1
BLANK* SIGNAL
transmitted to the
CX25870/871 and
received as an input.
•
If the SLAVE pin is tied to GND, the state of the SLAVER bit dictates
whether the CX25870/871 is the timing master or timing slave by
controlling the direction of the HSYNC* and VSYNC* ports. In other
words, SLAVER determines whether the overall interface is master or
pseudo-master. The SLAVER bit allows the graphics controller vendor to
switch between master video timing and slave video timing through
software so long as SLAVE pin (#51) is low.
•
•
EN_BLANKO is low (= 0), signifying the CX25870/871's BLANK* port
is an input.
EN_DOT = 1 telling the CX25870/871 to use the BLANK* signal it is
receiving to determine where active video starts (rising edge of BLANK*)
and uses HACTIVE register to determine the start of the blanking region.
EN_OUT = 1 ensures there is a clock output (CLKO) from the
CX25870/871 and also enables HSYNC* and VSYNC* outputs.
•
Table 1-9. Pseudo-Master Interface without a BLANK* Signal
SLAVER (Bit 5 of
0xBA) ORed with
Slave Pin
EN_BLANKO (MSb
of Register 0xC6)
EN_DOT (Bit 6 of
Register 0xC6)
EN_OUT (LSb of
Register 0xC4)
Interfaced Used
PSEUDO MASTER
BLANK* is NOT
included as part of
the interface.
1
1
0
1
100381B
Conexant
1-23
CONEXANT [ CONEXANT SYSTEMS, INC ]
