1.0 Functional Description
CX25870/871
1.3 Device Description
Flicker-Free Video Encoder with Ultrascale Technology
1.3.7.4 Slave Interface
In slave interface, no output signals are generated by the encoder. The
CX25870/871 relies strictly on the graphics controller to send clock and timing
signals to trigger when a new clock period, new line, and new frame starts.
Because no frequency reference signal is used (CLKO), the master device must
pre-program the encoder with an appropriate register set so the CX25870/871
expects data at the specific digital pixel rate prior to actually receiving the data. In
addition, the timing signals must be shaped so they adhere to the appropriate slave
interface timing diagrams illustrated in Chapter 4.0. Due to the added complexity
of this interface, Conexant recommends its use only as a final option.
The slave interface is illustrated in Figure 1-7 below using the graphics
controller as the master device and S-Video and 2 Composite ports as the video
outputs.
Figure 1-7. Operating the CX25870/871 in Slave Interface
Clock
Composite #1
Luma
CLKI
Cx25870/
CX25871
RGB or
Chroma
Graphics
Controller
YCrCb
Composite #2
HSYNC*
VSYNC*
BLANK*
100381_056
A minimum of 11 inputs (CLKI, HSYNC*, VSYNC*, and P[7:0]) are
required for this configuration. The amount of inputs will increase to 15 (without
BLANK*) or 16 (with BLANK*) if 24-bit multiplexed RGB mode is chosen as
the Input Pixel Mode (i.e., IN_MODE[3:0] = 0000) by the designer.
It is highly recommended that the device operate in master or pseudo-master
interface to ensure that the input and output video streams remain synchronized.
If either the master device, supplying the HSYNC* and VSYNC* inputs, or the
encoder, which receives the data, is not correctly programmed, the output image
will lose lock with the input. By running the CX25870/871 in either clock master
interface, any timing errors that occur can be absorbed to some extent by the
expansive on-board FIFO.
1-20
Conexant
100381B
CONEXANT [ CONEXANT SYSTEMS, INC ]
