CX11656 HomePlug 1.0 PHY Data Sheet
Table 2-2. CX11656 PHY Hardware Signal Definitions (Continued)
Signal Name
Pin
I/O
I/O Type
Analog Front End Interface
Signal Name/Description
ADC_CLK
DAC_CLK
TX_EN
RX_EN
ADIO[9:0]
71
74
76
77
O
O
O
O
Ot1
Ot1
Ot1
Ot1
ADC Clock. ADC clock output to the Analog Conversion IC.
DAC Clock. DAC clock output to the Analog Conversion IC.
Analog Front End Transmit Enable. Transmit Enable signal
Analog Front End Receive Enable. Receive Enable signal
94, 93, 92,
90, 87, 86,
84, 82, 81,
80
I/O
It/Ot12
Analog/Digital I/O. ADC and DAC Data. Multiplexed parallel interface
to Analog Conversion IC.
AGC[7:0]
106, 105,
103, 102,
100, 98, 97,
96
O
O
Ot1
Ot1
AGC Gain Select. Gain control driven by the CX11656 to set the AGC
level.
ADC_CAL
67
ADC Calibrate. This pin must remain low during normal operation of
the ADC. It is pulsed high to request a calibration cycle. The
ADC_CAL minimum pulse width is 4 clock cycles. While this signal is
high the ADC calibration registers are cleared and the calibration
control circuitry is reset. The ADC_CAL pulse will go high 217 clock
cycles (2.6 ms) after power on reset drops, and will remain high for the
required 4 clock cycles.
AGCENC_N
69
I
It
AGC Encode. An inactive signal (logic 1) applied to this input selects
unitary AGC format. An active signal (logic 0) applied to this input
selects encoded AGC format.
Test Access Port (Reserved)
TCK
TDI
TMS
TDO
114
120
124
116
129
I
I
I
O
I
It
It
It
Test Clock. Test Clock for the IEEE 1149.1 JTAG Port.
Test Data In. Data In for the IEEE 1149.1 JTAG Port.
Test Mode Select. Test Mode Select for the IEEE 1149.1 JTAG Port.
Test Data Out. Data Out for the IEEE 1149.1 JTAG Port.
Ot1
It
Test Reset. This pin will be used to reset the TAP controller. It should
TRST_N
be connected to ground when the JTAG port is not in use.
System Control
RESET_N
CLKIN
44
49
I
I
It
Reset. Resets logic circuitry, but not clock circuitry. Reset is active low
and should be held low for a minimum of 100 ns.
Ix
Clock Input. 100 MHz clock input driven by an external oscillator or
AFE. Note: CLKIN connects directly to the +1.8 V core of the IC and
does not connect to the +3.3 V I/O ring. Therefore, this pin is not +3.3
or 5 V tolerant.
CLKOUT
48
O
I
Ox
It
Clock Output. 100 MHz clock output. This pin should be left as NO
CONNECT.
MDI_ADRSEL[1]/
SPIS_SDI,
137,
139
MDI PHY Address Selection. MDI_ADRSEL[1:0] is the address
select used to compare against the upper two bits of the MDI Address.
These pins share function with SPIS_SDI and SPIS_CS_N and should
be pulled-up or down with external resistors to set the appropriate
value which is read by the CX11656 during power up.
MDI_ADRSEL[0]/
SPIS_CS_N
MDI_SPIS_N
126
141
I
I
It
It
Management Data Interface/Serial Peripheral Interface Slave
Select. When asserted low, MDI_SPIS_N selects which PHY
management signals are active.
Media Independent Interface/General Purpose Serial Interface
Select. When asserted low, MII_GPSI_N selects which PHY data
interface signals are active.
MII_GPSI_N
TEST1
TEST2
NC
111
112
131
I
I
It
It
Factory Test Pin 1. Tie to I/O Ground.
Factory Test Pin 2. Tie to I/O Ground.
No Connect.
102069A
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