CX11656 HomePlug 1.0 PHY Data Sheet
Table 2-2. CX11656 PHY Hardware Signal Definitions
Signal Name
Pin
I/O
I/O Type
Media Independent Interface (MII)
These pins are multiplexed with the GPSI pins and are selected when MII_GSPI_N signal is at VDD.
Signal Name/Description
MII_RX[3:0]
O
Ot1
MII Receive Data. Data is transferred from the CX11656 to the
external MAC across these four lines, MII_RX[3:0], one nibble at a
time.
27, 29, 31,
33
MII_RXCLK/
22
25
18
O
O
O
I
Ot1
Ot1
Ot1
It
MII Receive Clock. MII_RXCLK outputs a continuous 25 MHz clock to
GPSI_RXCLK
the external MAC.
MII_RXDV/
MII Receive Data Valid. When asserted high, MII_RXDV indicates
GPSI_TXBSY
that the incoming data on the MII_RX[3:0] pins are valid.
MII_RX_ER/
MII Receive Error. When asserted high, MII_RX_ER indicates to the
GPSI_RXD
external MAC that an error has occurred during the frame reception.
MII_TX[3:1]
MII_TX0/GPSI_TXD
4, 6, 8
11
MII Transmit Data. Data is transferred to the CX11656 from the
external MAC across these four lines (MII_TX[3:0]) one nibble at a
time.
MII_TXCLK/
14
12
16
O
I
Ot1
It
MII Transmit Clock. MII_TXCLK outputs a continuous 25MHz clock to
GPSI_TXCLK
the external MAC.
MII_TXEN/
MII Transmit Enable. This signal indicates to the CX11656 that valid
GPSI_TXEN
data is present on the MII_TX[3:0] pins.
MII Transmit Error. MII_TX_ER is activated by the external host
controller when an error condition is detected during packet
transmission. The CX11656 will ignore any MII transmission within
which MII_TX_ER is asserted. MII_TX_ER is ignored if MII_TXEN is
not asserted.
MII_TX_ER
I
It
MII_CRS/
42
40
O
O
Ot1
Ot1
MII Carrier Sense. When asserted high, MII_CRS indicates to the
external host that traffic is present on the powerline and the host
should wait until the signal goes invalid before sending additional data.
This signal is an asynchronous output signal.
MII Collision Detect. This signal indicates to the external host that a
collision has occurred on the MII interface. This signal is an
asynchronous output signal.
GPSI_RXEN
MII_COL/
GPSI_COL
MII Management Data Interface (MDI)
These pins are multiplexed with the SPIS_SDO and SPIS_SCLK signals and are selected when MDI_SPIS_N is at VDD.
MII_MDIO/
SPIS_SDO
135
133
I/O
I
It/Ot1
It
MII Management Data Output. MII_MDIO is the bidirectional signal
that carries the data for the Management Data Interface.
MII_MDCLK/
MII Management Data Clock. MII_MDCLK is the clock reference for
SPIS_SCLK
the MII_MDIO signal.
102069A
Conexant Proprietary and Confidential Information
2-5
CONEXANT [ CONEXANT SYSTEMS, INC ]
