CX11656 HomePlug 1.0 PHY Data Sheet
Table 2-2. CX11656 PHY Hardware Signal Definitions (Continued)
Signal Name
Pin
I/O
I/O Type
General Purpose Serial Interface (GPSI)
These pins are multiplexed with the MII pins and are selected when MII_GSPI_N signal is at VSS.
Signal Name/Description
MII_RX_ER/
18
O
O
I
Ot1
Ot1
It
GPSI Receive Data. GPSI_RXD carries data received from the
powerline and delivers to the external host. Data is driven on the
falling edge of the GPSI_RXCLK.
GPSI Receive Clock. GPSI_RXCLK is the timing reference for the
serial data transfer from the CX11656 to the external host. This clock
operates at 10 MHz.
GPSI Transmit Data. GPSI_TXD carries data transmitted from the
external host to the CX11656 for transmission over the powerline.
Data is latched on the falling edge of the GPSI_TXCLK.
GPSI_RXD
MII_RXCLK/
22
GPSI_RXCLK
MII_TX0/GPSI_TXD 11
GPSI_TXD
MII_TXCLK/
14
O
Ot1
GPSI Transmit Clock. This signal is the timing reference for the serial
data transfer from the external host to the CX11656. This clock
operates at 10 MHz.
GPSI_TXCLK
MII_CRS/
42
12
25
O
I
Ot1
It
GPSI Receive Enable. When asserted high, GPSI_RXEN indicates
GPSI_RXEN
valid data is on the GPSI_RXD line.
MII_TXEN/
GPSI Transmit Enable. When asserted high, GPSI_TXEN indicates
GPSI_TXEN
when the external host is providing valid data on GPSI_TXD.
MII_RXDV/
O
Ot1
GPSI Transmit Busy. GPSI_TXBSY is asserted within 120 GPSI
clocks after GPSI_TXEN indicates a TX frame is being sent by the
local host. GPSI_TXBSY stays true until the entire TX frame is loaded
into an internal buffer AND a new buffer is allocated to the GPSI TX
interface. This signal should be monitored by the GPSI TX host. A new
GPSI TX frame should not be sent until GPSI_TXBSY returns to false
to prevent TX buffer overflows. GPSI_TXBSY is an asynchronous
output signal.
GPSI_TXBSY
MII_COL/
40
O
Ot1
GPSI Collision Detect. GPSI_COL is driven false in GPSI mode.
GPSI_COL
SPI Slave Port
Selected when MDI_SPIS_N signal is at VSS.
MII_MDIO/
135
137
133
139
O
Ot1
It
SPI Slave Data Out. SPIS_SDO is the SPI data from the CX11656 to
SPIS_SDO
the external host.
MDI_ADRSEL[1]/
SPIS_SDI
I
SPI Slave Data In. SPIS_SDI is the SPI data from the external host
to the CX11656. This pin is shared with the MDI_ADRSEL[1].
MII_MDCLK/
I
It
SPI Slave Clock. SPIS_SCLK is the timing reference signal for
SPIS_SCLK
SPI_SDI and SPI_SDO.
MDI_ADRSEL[0]/
SPIS_CS_N
I
It
SPI Slave Chip Select. When asserted low, SPIS_CS_N enables SPI
data transfers on the CX11656. This pin is shared with the
MDI_ADRSEL[0].
SPI Master Port (Configuration PROM Interface)
SPI Master Data Out. SPI_DO is the CX11656 configuration data
SPI_DO
SPI_DI
59
57
54
52
O
Ot1
from the CX11656 to the external E 2 PROM.
I
It
SPI Master Data In. SPI_DI is the CX11656 configuration data from
the external E 2 PROM to the CX11656.
SPI_CLK
SPI_CS
O
O
Ot1
Ot1
SPI Master Clock. SPI_CLK is the timing reference signal for SPI_DI
and SPI_DO.
SPI Master Chip Select. When asserted high, SPI_CS enables data
transfers on the SPI Master Interface.
LED Control
Collision Detection. LED0_N is asserted low for 9–10 ms upon
LED0_N
LED1_N
61
63
O
O
Ot1
Ot1
detection of a collision.
LED1Activity Detection. LED1_N is asserted low for 9–10 ms upon
the receipt of a properly addressed unicast or broadcast frame or the
transmission of a frame.
Link Detection. LED2_N is asserted low when initialization is
LED2_N
65
O
Ot1
complete successfully and “network” is established.
2-6
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