CX11656 HomePlug 1.0 PHY Data Sheet
3.
CX11656 Functional Description
The interfaces that provide data, status, and control to and from the CX11656 include:
•
External host interface provided via the Media Independent Interface (MII) format
(described by IEEE 802.3u, Clause 22) or a General Purpose Serial Interface (GPSI)
•
Management control provided via the Management Data Interface (MDI) or the
Serial Peripheral Interface (SPI)
•
•
•
•
Analog Front End interface
LEDs indicating network status
Optional EEPROM interface providing a path to initialize the CX11656
The JTAG port implements the IEEE 1149.1 Standard Test Access Port and
Boundary Scan Architecture.
A block diagram of the CX11656 PHY is shown in Figure 3-1.
Figure 3-1. CX11656 PHY Block Diagram
LEDs
CX11656
ROM
ROM
MDI
or SPI
Configuration
Registers
RISC
Link
PHY
Seq
uProcessor Core
Sequencer
ADIO[9:0]
AGC [7:0]
PHY
Core
AFE
Logic
MDII
or GPSI
MII/GPSI
Interface
Interface
DMA
PHY
Arbiter
FIFOs
DMA
TEST
JTAG
Buffer
RAM
EEPROM
SPI
Master
Interface Block
MAC
PHY
102069_005
102069A
Conexant Proprietary and Confidential Information
3-1
CONEXANT [ CONEXANT SYSTEMS, INC ]
