CX11656 HomePlug 1.0 PHY Data Sheet
Figure 2-1. CX11656 PHY Hardware Interface Signals - 144-Pin LQFP
49
48
71
74
76
77
67
69
100 MHz Clock Input
CLKIN
ADC_CLK
DAC_CLK
TX_EN
100 MHz Clock Output
CLKOUT
RX_EN
44
111
112
RESET_N
TEST1
TEST2
ADC_CAL
AGCENC_N
Reset Control
94
93
92
90
87
86
84
82
81
80
ADIO9
ADIO8
ADIO7
ADIO6
ADIO5
ADIO4
ADIO3
ADIO2
ADIO1
ADIO0
AFE
Interface
131
NC
NC
27
29
31
33
22
25
18
4
MII_RX3
MII_RX2
MII_RX1
MII_RX0
MII_RXCLK/GPSI_RXCLK
MII_RXDV/GPSI_TXBSY
MII_RX_ER/GPSI_RXD
MII_TX3
Shared
MMII/GSPI/SPI
Interface
106
105
103
102
100
98
AGC7
AGC6
AGC5
AGC4
AGC3
AGC2
AGC1
AGC0
6
8
MII_TX2
MII_TX1
MII_TX0/GPSI_TXD
MII_TXCLK/GPSI_TXCLK
MII_TXEN/GPSI_TXEN
MII_TX_ER
MII_CRS/GPSI_RXEN
MII_COL/GPSI_COL
MII_MDIO/SPIS_SDO
MII_MDCLK/SPIS_SCLK
MII_GPSI_N
MDI_ADRSEL[1]/SPIS_SDI
MDI_ADRSEL[0]/SPIS_CS_N
MDI_SPIS_N
11
14
12
16
42
40
135
133
141
137
139
126
AGC IC Interface
LED Interface
97
96
61
63
65
LED0_N
LED1_N
LED2_N
5
VSS_C
VSS_C
VSS_C
VSS_C
VSS_C
VSS_C
VSS_C
VSS_C
VSS_C
VSS_C
VSS_C
VSS_C
VSS_C
VSS_C
VSS_C
VSS_C
VSS_C
VSS_C
VSS_C
VSS_C
VSS_C
VSS_C
VSS_C
VSS_C
VSS_C
VSS_C
VSS_C
VSS_C
VSS_C
VSS_C
VSS_C
VSS_C
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_IO
VSS_Q
VSS_Q
VSS_Q
10
19
59
57
54
52
20
SPI_DO
26
CX11656
SPI Master Port
Interface
SPI_DI
30
SPI_CLK
SPI_CS
HomePlug 1.0
PHY
34
36
114
120
124
116
129
41
TCK
144-PIN LQFP
46
TDI
JTAG Test
Interface
47
TMS
55
TDO
(Reserved)
56
TRST_N
58
1
2
62
VDD_C
VDD_C
VDD_C
VDD_C
VDD_C
VDD_C
VDD_C
VDD_C
VDD_C
VDD_C
VDD_C
VDD_C
VDD_C
VDD_C
VDD_C
VDD_C
VDD_C
VDD_C
VDD_C
VDD_C
VDD_C
VDD_C
VDD_C
VDD_C
VDD_C
VDD_C
VDD_C
VDD_C
66
7
72
13
75
17
85
23
88
24
101
108
113
117
118
119
127
128
134
138
143
144
9
28
32
37
38
43
50
+1.8 V
53
Core Power
60
68
73
78
99
104
109
115
121
122
123
125
132
140
35
45
70
83
107
142
21
89
130
3
39
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
64
79
95
110
136
+3.3 V
I/O and Quiet
Power
15
51
91
VDD_Q
VDD_Q
VDD_Q
102069_003
2-2
Conexant Proprietary and Confidential Information
102069A