CN8478/CN8474A/CN8472A/CN8471A
2.0 Host Interface
Multichannel Synchronous Communications Controller (MUSYCC™)
2.2 PCI Configuration Registers
Register 15, Address 3Ch
Table 2-16. Register 15, Address 3Ch
Bit
Field
Reset
Value
Name
Type
RO
Description
31:16
15:8
Reserved
0
Unused.
Interrupt Pin
02h
RO
Defines which PCI interrupt pin Function 1 uses. 02h means
MUSYCC uses pin INTB* for interrupts sourced by devices
connected to EBUS.
7:0
Interrupt Line
0
RW
Communicates interrupt line routing. System initialization
software writes a value to this register indicating which host
interrupt controller input is connected to MUSYCC’s INTB* pin.
NOTE(S): An active-low signal is denoted by a trailing asterisk (*).
2.2.3 PCI Reset
MUSYCC resets all internal functions when it detects the assertion of the PRST*
signal line. Upon reset, the following occurs:
•
•
All PCI output signals go to three-state immediately and asynchronously
with respect to the PCI clock input, PCLK.
All EBUS output signals go to three-state immediately and asynchronously
with respect to the EBUS clock output, ECLK.
•
•
•
•
All writable register bits are set to 0.
All PCI data transfers terminate immediately.
All serial data transfers terminate immediately.
MUSYCC disables and responds only to PCI configuration cycles.
2.2.4 Host Interface
After a hardware reset, the PCI configuration space within MUSYCC needs to be
configured by the host with the following information:
For Function 0:
•
•
•
•
•
•
Base address register
Fast back-to-back enable/disable
SERR* signal driver enable/disable
Parity error response enable/disable
Bus mastering enable/disable
Memory space access enable/disable
For Function 1:
•
•
•
Base address register
Parity error response enable/disable
Memory space access enable/disable
Function 0 provides services to the serial interfaces in MUSYCC; Function 1
provides services to the EBUS interface in MUSYCC.
After the configuration spaces are configured, MUSYCC can master the PCI
bus or provide slave-mode access to the host.
100660E
Conexant
2-17