CN8478/CN8474A/CN8472A/CN8471A
2.0 Host Interface
Multichannel Synchronous Communications Controller (MUSYCC™)
2.2 PCI Configuration Registers
When MUSYCC requests the PCI bus, it needs the bus to transfer data
between an internal FIFO buffer and shared memory across the PCI bus with
either a read or a write access. While MUSYCC waits for the bus to be granted,
and then while MUSYCC transfers the data, another equal-sized internal FIFO
buffer is simultaneously being filled or emptied at the serial interface. When
MUSYCC requests the bus, it has data to transfer, and also has a finite amount of
time (which is directly related to the speed of the serial line clock) before a
separate FIFO buffer at the serial interface overflows or underflows.
For an application with many logical channels, MUSYCC requires a new
access cycle on the PCI bus more frequently than an application with fewer
logical channels. If FIFO buffer space is evenly distributed across all channels,
more channels result in less FIFO buffer space per channel, and FIFO buffer
space must be cleared more frequently.
Conversely, an application with high data rate serial interfaces requires a new
access cycle on the PCI bus more frequently than an application with a low data
rate serial interface, because the FIFO buffer fills faster in the former.
Acquiring the PCI bus requires having to deal with arbitration latency, which
is defined as the number of PCI clock cycles a master must wait after asserting its
REQ* and before asserting the GNT* signal. This number is a function of the
system’s arbitration algorithm and takes into account the sequence in which
masters are given access to the bus and the latency timer of each master.
Arbitration latency is also affected by the loading of the system and how
efficiently the bus is being utilized.
The master’s latency timer specifies the maximum number of PCI clock cycles
that the master can (and in the case of MUSYCC, will) keep the bus after starting
the access cycle by asserting its FRAME*. The latency timer also ensures that the
master has a minimum time slot for it to own the bus, but places an upper limit on
how long it will own the bus. In MUSYCC, the Latency Timer is reset to 0 on
PRST* (PCI reset).
Once the bus is acquired and bursting begins, PCI throughput becomes the
point of focus. MUSYCC is capable of multi-dword bursts (read or write). As
each FIFO buffer for a logical channel and direction is serviced on the PCI,
MUSYCC relinquishes and then reacquires the bus to service the FIFO buffer of
the next logical channel. If more logical channels are serviced, bus turnover is
increased, which decreases throughput (but does not necessarily affect service). If
fewer logical channels are serviced, bus turnover decreases, and that increases
throughput (but not necessarily to the benefit of channel processing).
Refer to Chapter 3 of the PCI Local Bus Specification, Revision 2.1, for a
description of bandwidth and latency considerations.
2.2.6.1 PCI Bus Latency
The latency that a PCI master encounters as it tries to gain access to the PCI bus
has three components:
1. Arbitration latency: usually 2 clock cycles for a high priority device, but is
added into the total latency time only if the bus is idle when a device
requests it, otherwise, it overlaps with the bus acquisition latency.
2. Bus acquisition latency: length of time a device must wait for the bus to
become free.
3. Target latency: length of time the selected target takes to assert TRDY* for
the first data transfer.
100660E
Conexant
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CONEXANT [ CONEXANT SYSTEMS, INC ]
