2.0 Host Interface
CN8478/CN8474A/CN8472A/CN8471A
2.2 PCI Configuration Registers
Multichannel Synchronous Communications Controller (MUSYCC™)
Register 3, Address 0Ch
Table 2-13. Register 3, Address 0Ch
Bit
Reset
Value
Name
Field
Type
Description
31:24
23:16
Reserved
0
RO
RO
Unused.
Header Type
80h
MUSYCC is a multifunction device with the standard layout of
configuration register space.
15:0
Reserved
0
RO
Unused.
Register 4, Address 10h
Table 2-14. Register 4, Address 10h
Bit
Reset
Value
Name
Field
Type
RW
Description
31:20
EBUS—Function 1
0
Allows for 1 MB bounded PCI bus address space to be blocked
off as MUSYCC expansion bus space. MUSYCC responds as a
PCI slave with DEVSEL* to all memory cycles whose non-zero
address bits 31:20 match the value of bits 31:20 of this register,
with memory space enabled in Function 1 Register 1, memory
space bit field.
Base Address Register
Reads to addresses within this space that are not
implemented. Reads back 0; writes have no effect.
PCI cycles to this space will be mapped to read or write
cycles on the expansion bus.
19:4
0
RO
When appended to bits 31:20, specifies a 1 MB bound memory
space. 1 MB is the only size of address space that a MUSYCC
function can be assigned.
3
0
0
RO
RO
Expansion bus memory space is not prefetchable.
2:1
Means MUSYCC expansion bus space can be located anywhere
in 32-bit address space.
0
0
RO
Means this base register is a memory space base register, as
opposed to I/O mapped.
NOTE(S): An active-low signal is denoted by a trailing asterisk (*).
Register 5–14,
Addresses 14h–38h
Table 2-15. Registers 5 through 14–Addresses 14h through 38h
Bit
Field
Reset
Value
Name
Type
Description
31:0
Reserved
0
RO
Unused.
2-16
Conexant
100660E
CONEXANT [ CONEXANT SYSTEMS, INC ]
