CN8478/CN8474A/CN8472A/CN8471A
2.0 Host Interface
Multichannel Synchronous Communications Controller (MUSYCC™)
2.2 PCI Configuration Registers
Table 2-11. Register 1, Address 04h (2 of 2)
Bit
Field
Reset
Value
Name
Command
Type
Description
15:7
6
0
0
RO
Unused.
RW
Parity error response.
This bit controls MUSYCC’s Function 1 response to parity
errors.
If 1, MUSYCC will take normal action when a parity error is
detected on a cycle with Function 1 as the target.
If 0, MUSYCC will ignore parity errors.
5:2
1
0
0
RO
Unused.
RW
Memory Space access control.
If 1, enables MUSYCC to respond to Function 1 memory
space access cycles.
If 0, disables MUSYCC’s response.
0
0
RO
I/O space accesses. MUSYCC does not contain any I/O space
registers.
NOTE(S): An active-low signal is denoted by a trailing asterisk (*).
Register 2, Address 08h
This location contains the Class Code and Revision ID registers. The Class Code
register contains the Base Class Code, Sub-Class Code, and Register Level
Programming Interface fields, used to specify the generic functions of MUSYCC.
The Revision ID register denotes the version of silicon.
Table 2-12. Register 2, Address 08h
Bit
Reset
Value
Name
Field
Type
Description
Base Class Code: Bridge Device.
31:24
06h
80h
0
RO
RO
RO
23:16
Sub-Class Code Type: Other Bridge Device.
Class Code
15:8
Register Level Programming Interface: Indicates there is nothing
special about programming MUSYCC.
Revision ID(1)
7:0
01h
RO
Denotes the revision number of MUSYCC. Rev A = 0Ah,
Rev B = 0Bh, Rev C = 0Ch, etc.
NOTE(S):
(1)
Registers shared between Function 0 and 1.
100660E
Conexant
2-15
CONEXANT [ CONEXANT SYSTEMS, INC ]
