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CN8474AEPF 参数 Datasheet PDF下载

CN8474AEPF图片预览
型号: CN8474AEPF
PDF下载: 下载PDF文件 查看货源
内容描述: 多通道同步通信控制器( MUSYCC ™ ) [Multichannel Synchronous Communications Controller (MUSYCC?)]
分类和应用: 通信控制器
文件页数/大小: 221 页 / 2104 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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CN8478/CN8474A/CN8472A/CN8471A  
5.0 Memory Organization  
Multichannel Synchronous Communications Controller (MUSYCC™)  
5.2 Descriptors  
5.2.6 Interrupt Handling  
5.2.6.1 Initialization  
Interrupt management resources are automatically reset upon the following:  
Hardware reset  
Soft-chip reset service request  
Global initialization service request  
Read Interrupt Queue Descriptor service request  
Direct memory write to Interrupt Queue Pointer  
Direct memory write to Interrupt Queue Length  
MUSYCC uses two interrupt queues: one is internal to MUSYCC and is  
controlled exclusively by the interrupt controller logic; the other is the Interrupt  
Queue in shared memory, which is allocated and administered by the host, but  
written to by MUSYCC.  
Upon initialization, the data in the status descriptor is reset to 0s, indicating  
the first location for next descriptor, the queue is not full, and no descriptors are  
in the queue. Any existing descriptors in the internal queue are discarded.  
The Interrupt Status Descriptor stores the location of the next descriptor to be  
read by the host, a queue full indicator, and a count of interrupts last written into  
shared memory since the last read of the Interrupt Status Descriptor.  
The host must allocate sufficient shared memory space for the Interrupt  
Queue. Up to 32,768 dwords of queue space are accessible by MUSYCC, setting  
the upper limit for the queue size. MUSYCC requires a minimum of two dwords  
of queue space, setting the lower limit for the queue size.  
The host must store the pointer to the queue and the queues length in dwords  
in MUSYCC within the Interrupt Queue Descriptor register. This is done by  
issuing the appropriate service request to MUSYCC. As MUSYCC takes in the  
new values, it automatically resets the controller logic as indicated above. This  
mechanism can also be used to switch interrupt queues while MUSYCC is in full  
operation.  
5.2.6.2 Interrupt  
Descriptor Generation  
Interrupt conditions are detected in both error and non-error cases. MUSYCC  
makes a determination based on channel group, channel, and device  
configuration, whether reporting the condition is to be masked or whether an  
Interrupt Descriptor is to be sent to the host. If the interrupt is not masked,  
MUSYCC generates a descriptor and stores it internally prior to transfer to the  
Interrupt Queue in shared memory.  
The internal queue is capable of holding 128 descriptors while MUSYCC  
arbitrates to master the PCI bus and transfer the descriptors into the Interrupt  
Queue in shared memory.  
As the PCI bus is mastered and after descriptors are transferred to shared  
memory, MUSYCC updates the Interrupt Status Descriptor. In making the  
INTCNT field in the descriptor non-0, MUSYCC asserts the PCI INTA* signal  
line.  
If, during the transfer of descriptors, the Interrupt Queue in shared memory  
becomes full, MUSYCC stops transferring descriptors until the host indicates  
more descriptors can be written out. MUSYCC indicates it cannot transfer more  
descriptors into shared memory by setting the bit field INTFULL in the Interrupt  
Status Descriptor. MUSYCC has enough internal space to store 128 additional  
descriptors.  
100660E  
Conexant  
5-45  
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