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CN8474AEPF 参数 Datasheet PDF下载

CN8474AEPF图片预览
型号: CN8474AEPF
PDF下载: 下载PDF文件 查看货源
内容描述: 多通道同步通信控制器( MUSYCC ™ ) [Multichannel Synchronous Communications Controller (MUSYCC?)]
分类和应用: 通信控制器
文件页数/大小: 221 页 / 2104 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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6
6.0 Basic Operation  
6.1 Reset  
There are five levels of reset state:  
Hard PCI Reset  
Soft Chip Reset  
Soft Group Reset  
Channel Activation  
Channel Deactivation  
There are two ways to assert a reset:  
1. Assert the PCI reset signal pin, PRST*.  
2. Assert a service request through the host interface to perform the soft chip  
reset, soft group reset, channel activation, or channel deactivation.  
6.1.1 Hard PCI Reset  
The PCI reset is the most thorough level of reset in MUSYCC. All subsystems  
enter into their initial states. PCI reset is accomplished by asserting the PCI  
signal, PRST*.  
The PRST* signal is an asynchronous signal on the PCI bus. The reset signal  
can be activated in several ways. The system must always assert the reset signal  
on power-up. Also, a host bus to a PCI bus bridging device should provide a way  
for software to assert the reset signal. Additionally, software-controlled circuitry  
can be included in the system design to specifically assert the reset signal on  
demand.  
Asserting PRST* towards MUSYCC guarantees that data transfer operations  
and PCI device operations will not begin until MUSYCC has been properly  
initialized for operation. Upon entering the PCI reset state, MUSYCC outputs a  
three-stated signal on all output pins and stops activity on all subsystems  
including the host interface, serial interface, and expansion bus.  
A PCI reset signal in MUSYCC takes one PCI clock cycle to complete, after  
which the host can communicate with MUSYCC using the PCI configuration  
cycles.  
100660E  
Conexant  
6-1  
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