6
6.0 Basic Operation
6.1 Reset
There are five levels of reset state:
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Hard PCI Reset
Soft Chip Reset
Soft Group Reset
Channel Activation
Channel Deactivation
There are two ways to assert a reset:
1. Assert the PCI reset signal pin, PRST*.
2. Assert a service request through the host interface to perform the soft chip
reset, soft group reset, channel activation, or channel deactivation.
6.1.1 Hard PCI Reset
The PCI reset is the most thorough level of reset in MUSYCC. All subsystems
enter into their initial states. PCI reset is accomplished by asserting the PCI
signal, PRST*.
The PRST* signal is an asynchronous signal on the PCI bus. The reset signal
can be activated in several ways. The system must always assert the reset signal
on power-up. Also, a host bus to a PCI bus bridging device should provide a way
for software to assert the reset signal. Additionally, software-controlled circuitry
can be included in the system design to specifically assert the reset signal on
demand.
Asserting PRST* towards MUSYCC guarantees that data transfer operations
and PCI device operations will not begin until MUSYCC has been properly
initialized for operation. Upon entering the PCI reset state, MUSYCC outputs a
three-stated signal on all output pins and stops activity on all subsystems
including the host interface, serial interface, and expansion bus.
A PCI reset signal in MUSYCC takes one PCI clock cycle to complete, after
which the host can communicate with MUSYCC using the PCI configuration
cycles.
100660E
Conexant
6-1
CONEXANT [ CONEXANT SYSTEMS, INC ]
