CN8478/CN8474A/CN8472A/CN8471A
5.0 Memory Organization
Multichannel Synchronous Communications Controller (MUSYCC™)
5.2 Descriptors
Table 5-31. Interrupt Descriptor (3 of 4)
Bit
Field
Field
Name
Interrupt
Name
Value
Description
FCS(2)
19:16 ERROR[3:0]
9
V
V
V
V
V
V
V
V
Frame Check Sequence Error. Generated when received
HDLC frame is terminated with octet-aligned 7Eh flag, but
computed FCS does not match received FCS.
ALIGN(2)
10
Octet Alignment Error. Generated when message payload
size, after zero extraction, is not a multiple of 8 bits. This
generally occurs with an FCS error. This interrupt also
implies an FCS error. The FCS interrupt will not be
generated if the ALIGN interrupt is issued.
ABT(2)
LNG(2)
11
12
V
V
V
V
V
V
V
V
Abort Termination. Generated when received message is
terminated with an abort sequence—seven sequential
1s—instead of a specific closing flag – 7Eh.
Long Message. Generated when received message length
(after zero extraction) is greater than selected maximum
message size. Message reception is terminated and not
transferred to shared memory.
13
SHT
V
V
V
V
V
V
V
V
Short Message. Generated when received message length
(after zero extraction) is less than or equal to number of
bits in FCS field. The message data is not transferred to
shared memory.
14
15
SUERR
PERR
SS7 Signal Unit Error Rate Interrupt. Generated when in
SS7 mode and error monitor, SUERM, value rises past the
threshold value, SUET.
PCI Bus Parity Error. Generated when MUSYCC detects a
parity error on data transferred into MUSYCC either from
another PCI agent writing into MUSYCC, or from MUSYCC
reading data from shared memory. This error is specific to
the data phase of a PCI transfer while MUSYCC is receiving
data. Note: PCI system error signal, SERR*, is ignored by
MUSYCC. NOTE: To mask the PERR interrupt, MUSYCC’s
PCI Configuration Space, Function 0, Register 1, Parity
Error Response field must be set to 0.(3)
15
ILOST
0
1
ILOST
No interrupts have been lost.
Interrupt Lost. Generated when internal interrupt queue is
full, and additional interrupt conditions are detected.
Because MUSYCC cannot store the newest interrupt
descriptors, it discards the new interrupts and overwrites
this bit in the last interrupt in an internal queue prior to that
interrupt being transferred out to shared memory. The
integrity of the descriptor being overwritten is maintained.
100660E
Conexant
5-43
CONEXANT [ CONEXANT SYSTEMS, INC ]
