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CN8474AEPF 参数 Datasheet PDF下载

CN8474AEPF图片预览
型号: CN8474AEPF
PDF下载: 下载PDF文件 查看货源
内容描述: 多通道同步通信控制器( MUSYCC ™ ) [Multichannel Synchronous Communications Controller (MUSYCC?)]
分类和应用: 通信控制器
文件页数/大小: 221 页 / 2104 K
品牌: CONEXANT [ CONEXANT SYSTEMS, INC ]
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5.0 Memory Organization  
CN8478/CN8474A/CN8472A/CN8471A  
5.2 Descriptors  
Multichannel Synchronous Communications Controller (MUSYCC™)  
Table 5-31. Interrupt Descriptor (4 of 4)  
Bit  
Field  
Field  
Name  
Interrupt  
Name  
Value  
Description  
14  
GRP[2]  
MSB of Group number.  
13:0  
BLEN[13:0]  
This field is relevant when EVENT field is EOB (Rx and Tx)  
or EOM (Rx only). For Rx, it is equal to the number of octets  
received. For Tx, it is the size of the buffer length targeted  
for transmission and not necessarily the number of octets  
transmitted. This field is 0 all other times.  
NOTE(S):  
(1)  
Receive EOB and Receive EOM are concurrent events and are reported as a single interrupt; whereas Transmit EOB and EOM  
are separate events and are reported as separate interrupts (two interrupt events).  
Interrupt names are also reported in an error field within a receive Buffer Status Descriptor which indicates the transfer status  
of a message currently being processed on a channel. The order of appearance in shared memory of a Buffer Status Descriptor  
and an Interrupt Descriptor carrying the same error condition information is indeterminate. The host should confirm that both  
an Interrupt Descriptor and a Buffer Status Descriptor reports the error condition.  
(2)  
(3)  
Previously existed in bit 14 of 8474, 8472.  
5.2.5.3 Interrupt Status  
Descriptor  
The Interrupt Status Descriptor is located in a fixed position within MUSYCCs  
internal registers. MUSYCC updates this descriptor after each transfer of  
interrupt descriptors from its internal queue to the Interrupt Queue in shared  
memory. The host must read this descriptor from MUSYCC registers before it  
processes any interrupts. The interrupt status descriptors contents are reset on  
hardware reset, soft chip reset, or when any field in the Interrupt Queue  
Descriptor is modified.  
Table 5-32 lists the details of the Interrupt Status Descriptor.  
Table 5-32. Interrupt Status Descriptor  
Bit  
Field  
Name  
Value  
Description  
31  
RSVD  
0
Reserved.  
30:16  
NEXTINT[14:0]  
Next Interrupt Index. 15-bit dword index from start of Interrupt Queue up to where the  
host has serviced Interrupt Descriptors.  
The host can read this value to get the location of the first unserviced descriptor in  
the queue. As the queue is circular, care must be taken to ensure roll-over cases at  
beginning and end of queue. Only the host updates this value. The NEXTINT is a  
read/write bit field. This is a 0-based number and equals the dword offset from Interrupt  
Queue Pointer.  
Interrupt Queue Not Full—shared memory.(1)  
Interrupt Queue Full—shared memory.(1)  
15  
INTFULL  
0
1
14:0  
INTCNT[14:0]  
Interrupt Count. 15-bit value indicates the number of interrupts pushed into the  
Interrupt Queue since the last reading of the Interrupt Status Descriptor. All writes to  
this bit field register are ignored.  
NOTE(S):  
(1)  
The INTFULL status is read—cleared bit field.  
5-44  
Conexant  
100660E  
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