Bt8370/8375/8376
2.0 Circuit Description
2.6 Clock Rate Adapter
Fully Integrated T1/E1 Framer and Line Interface
2.6 Clock Rate Adapter
The full function Clock Rate Adapter is included in all Bt8370 and Bt8375
devices. In the Bt8376, the CLADO output is not implemented.
The Clock Rate Adapter (CLAD) illustrated in Figures 2-21 and 2-22 uses an
input clock reference at a particular frequency (range 8 kHz to 16,384 kHz) to
synthesize an output clock (CLADO and JCLK) at a different frequency (range
1024 kHz to 16,384 kHz). The CLAD also controls the read or write pointers of
the elastic store by synthesizing a Jitter-attenuated Line rate Clock (JCLK); thus,
it is an integral part of the Jitter Attenuator (JAT). The CLAD input clock jitter
tolerance and jitter transfer functions are illustrated in Figures 2-9 and 2-10.
These diagrams are illustrated for various programmed loop filter gain values
(LFGAIN; addr 090).
N8370DSE
Conexant
2-39
CONEXANT [ CONEXANT SYSTEMS, INC ]
