Bt8370/8375/8376
3.17 System Bus Registers
Fully Integrated T1/E1 Framer and Line Interface
TSYN_NEG
Output Sync on Falling Edge Clock—Selects TSBCKI rising or falling edge clock signal for
TFSYNC or TMSYNC outputs. Opposite TSBCKI edge is used if TFSYNC or TMSYNC is
programmed as input.
0 = TFSYNC or TMSYNC rising edge output (falling edge input)
1 = TFSYNC or TMSYNC falling edge output (rising edge input)
When TFSYNC or TMSYNC is an input and configured for rising edge sampling,
TFSYNC or TMSYNC must be sampled low during the previous falling clock edge, then
sampled high at the rising clock edge. (Refer to Figure 5-5, SBI Timing: Setup and Hold Time
for RFSYNC/RMSYNC and TFSYNC/TMSYNC Input Signals and Table 5-6, Input Data Setup
and Hold Timing.)
TSB_ALIGN
TSB_CTR
Transmit System Bus Multiframe Aligns to Transmit Timebase—Allows multiframe
alignment located at TX timebase to pass across TSLIP and forces the corresponding
multiframe alignment onto the TSB timebase. Used primarily to pass CAS or MFAS alignment
located by the transmit online framer onto the TMSYNC output.
0 = TSB multiframe does not follow XMTR
1 = TSB multiframe aligned by XMTR
Force TSLIP to Center—Writing a 1 to TSB_CTR forces TSLIP read buffer pointer to its
initial delay condition, possibly forcing a change of transmit frame alignment if TSLIP is
configured in Elastic or Bypass modes. Writing a 0 has no effect. The processor must assert
TSB_CTR after configuration of the transmit slip buffer, after which, Bt8370/8375/8376
automatically recenters TSLIP buffer according to the configured mode. Centering TSLIP
does not effect TSLIP status reported in ISR5[addr 006].
0 = no effect
1 = force TSLIP to center
TSBI[1:0]
Transmit Slip Buffer Interface mode—Selects the configuration of the TSLIP buffer. The TSBI
determines the total buffer depth and initial delay conditions. While TSLIP is bypassed, TCKI
clocks the TSB input/output, and TSBCKI is ignored.
TSBI
00
Mode
Total Depth
2 Frame
Initial Delay
Conditions
Normal
0.5 to 1.5 Frames
Dependent on present depth, no
change of output frame.
01
10
11
Short
Elastic
Bypass
2 Frame
64 Bits
0 Bits
32 Bits
32 Bits
0 Bits
Reverts to normal upon slip
Recenters automatically upon slip
TSBCKI ignored
NOTE(S): Bypass requires system bus equal to line rate.
To guarantee the pointer is initialized properly in the slip buffer during Elastic Mode,
the following procedure can be applied:
1. Disable Slip Buffer
2. Center Slip Buffer
TSBI[1:0] = 11, TSB_CTR = 0
TSBI[1:0] = 11, TSB_CTR = 1
3. Set the Slip Buffer to Elastic mode TSBI[1:0] = 10, TSB_CTR = 0
3-118
Conexant
N8370DSE
CONEXANT [ CONEXANT SYSTEMS, INC ]
