Digitally Controlled Analog I/O Processor
6
MX839 PRELIMINARY INFORMATION
4
General Description
The device comprises four groups of related functions: variable attenuators, digital to analog converters, a multiplexed
analog to digital converter with multiplexer, clock generator and four 8-bit magnitude comparators with variable reference
levels. These functions are all controlled by the 'C-BUS' serial interface and are described below:
4.1 Variable Attenuators
The two variable attenuators have a range of 0 to -12dB and 0 to -6dB respectively and may be controlled independently.
4.2 Digital to Analog Converters
Three DACs are provided with default resolutions of 8 bits, which are defined at the initial chip reset. In this mode the
'C-BUS' data is transferred in a single byte. An option is provided to define any one or more of the DAC resolutions to be
10 bits, then the DAC requires the transfer of two 'C-BUS' data bytes.
The upper and lower DAC reference voltages are defined internally as AVDD and VSS respectively. The output voltage is
expressed as:
n
VOUT = AVDD x (DATA / 2 ) [Volts]
Where, n is the DAC resolution (8 or 10 bits) and DATA is the decimal value of the input code. For example: n = 8 and
binary code = 11111111 therefore DATA = 255
VOUT = AVDD x (255 / 256) [Volts]
Any one of the three DAC input latches might be loaded by sending an address/command byte followed by one or two
data bytes to the 'C-BUS' interface. The data is then latched and the static voltage is updated at the appropriate output.
When a DAC is disabled, its output is defined as open-circuit.
4.3 Analog to Digital Converter and A/D Clock Generator
A single successive approximation A/D is provided with four multiplexed inputs. After a general reset command $01, the
A/D converter subsystem is disabled. To start conversions the Clock Control ($D0) and A/D control ($D7) registers must
be written (refer to Tables 2,6, and 8). Please note that A/D channel 1 must be active for any other channel to work. Also
note that A/D control register bit 5 (READ ) should be set low prior to issuing a ‘READ A/D DATA x’ command to disable
conversions so the data being read does not change during the read which could otherwise result in erroneous data being
read. To re-enable conversions the A/D control register bit 5 (READ ) bit must be set back high.
The internal A/D clock frequency (f
) is generated with a programmable clock generator. Users have flexible
A/D_CLK
control of this clock signal via the Clock Control Register ($D0), DIVIDER set per Table 6, and the choice of an external
system clock signal or a dedicated crystal. f should be chosen not to exceed 1MHz.
A/D_CLK
Since the typical application is for monitoring slowly changing control voltages, a Sample and Hold circuit is not included
at the input of the A/D. Thus, for the analog to digital conversion to be accurate, the input signal should not change
significantly during the conversion time. For ‘n-bit’ accuracy (with a maximum error of 1LSB) the maximum signal ‘linear
rate of change,’ ‘S,’ is defined by:
AVDD fA/D_CLK
2n 1000 (n+2)
S =
[mV/PS]
where: n is the number of bits of accuracy with a maximum error of 1 LSB
fXTAL
where: fA/D_CLK
=
, DIVIDER is selected per Table 6.
DIVIDER
For Example: The most significant bits (n) of accuracy.
For (n = 6) bit accuracy with AV =5V and f
= 1MHz
= 1MHz
DD
A/D_CLK
S = 9.77 [mV/PS]
For (n = 8) bit accuracy with AV =5V and f
_
A/D CLK
DD
S = 1.95 [mV/PS]
For (n = 10) bit accuracy with AV =3.3V and f
= 1MHz
DD
A/D_CLK
S = 0.27 [mV/PS]
The input signal should therefore be band limited to ensure the maximum signal ‘linear rate of change’ is not exceeded for
the desired accuracy.
© 1998 MXxCOM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480164.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
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