Digitally Controlled Analog I/O Processor
10
MX839 PRELIMINARY INFORMATION
4.7.2 CLOCK CONTROL Register (Hex Address $D0)
This register controls the A/D clock divide ratio:
Reserved for future use. These bits should be set to '0'.
Bits 7 to 3
The Xtal input clock divide ratio, which sets the A/D sample clock frequency, is defined in the
following table.
DIVIDER
(Bit 2 - Bit 0)
Table 5: CLOCK CONTROL Register (Hex Address $D0)
Bit 2
Bit 1
Bit 0
Function
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Powersave
y1
y2
y4
y8
y16
y32
y64
Table 6: DIVIDER (Bit 2 - Bit 0)
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