High Speed GMSK Modem 4k to 64kbps
Page 13 of 20
MX589
4.4
Data Formats
The receive section of the MX589 works best with data which has a reasonably random structure --the data
should contain approximately the same number of ‘ones’ as ‘zeroes’ with no long sequences (>100 bits) of
consecutive ones or zeroes. Also, long sequences (>100 bits) of 10101010 ... patterns should be avoided.
For this reason, it is recommended that data be made random in some manner before transmission, for
example by exclusive-ORing it with the output of a binary pseudo-random pattern generator.
Where data is transmitted in bursts, each burst should be preceded by a preamble designed to allow the
receive modem to establish timing and level lock as quickly as possible. This preamble for BT=0.3 should be
at least 16 bits long, and should preferably consist of alternating pairs of ones and zeros i.e.
110011001100....; the eye of pattern 10101010 .... has the most gradual slope and will yield poor peak levels
for the RX circuits. For BT=0.5 the eye pattern of 10101010... has reduced intersymbol interference and may
be used as the preamble (DC Acq pin should be held high during preamble). See Fig. 6.
4.5
Acquisition and Hold Modes
The RXDCacq and PLLacq inputs must be pulsed High for about 16 bits at the start of reception to ensure
that the DC measurement and timing extraction circuits lock-on to the received signal correctly. Once lock
has been achieved, the above inputs should be taken Low again.
In most applications, there will be a DC step in the output voltage from the receiver FM discriminator due to
carrier frequency offsets as channels are changed or when the remote transmitter is turned on.
The MX589 can tolerate DC offsets in the received signal of at least ±0.5V with respect to VBIAS, (measured at
the RX Feedback pin). However, to ensure that the DC offset compensation circuit operates correctly and
with minimum delay, the Low to High transition of the RXDCacq and PLLacq inputs should occur after the
mean input voltage to the MX589 has settled to within about 0.1V of its final value.
Note: This can place restrictions on the value of any series signal coupling capacitor.
As well as using the RX Hold input to freeze the Level Measuring and Clock Extraction circuits during a signal
fade, it may also be used in systems which use a continuously transmitting control channel to freeze the RX
circuitry during transmission of a data packet, allowing reception to resume afterwards without losing bit
synchronization. To achieve this, the MX589 Xtal clock needs to be accurate enough that the derived
RXClock output does not drift by more than about 0.1 bit time from the actual received data-rate during the
time that the RXHold input is ‘Low’.
However; the RXDCacq input may need to be pulsed High for 2 bit durations to re-establish the level
measurements if the RXHold input is Low for more that a few hundred bit-times (exact number depends on
system crystal tolerances).
The voltages on the Doc1 and Doc2 pins reflect the average peak positive and negative excursions of the
(filtered) receive signal, and could therefore be used to derive a measure of the data signal amplitude.
Note: These pins are driven from very high-impedance circuits, so that the DC load presented by any
external circuitry should exceed 10MΩ to VBIAS
.
2001 MX-COM, Inc.
www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054
Doc. # 204800103.011
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
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