FRS Signalling Processor
CMX882
1.6.20.1 PROGRAMMING REGISTER Block 0 – Modem Configuration:
$C8 (P0.0-1) MSK Frame Sync
15
1
14
1
13
0
12
0
11
10
9
8
7
6
5
4
3
2
1
0
Bit:
P0.0
0
0
MSK Frame Sync LSB
MSK Frame Sync MSB
P0.1
0
1
0
0
Bits 7 to 0 set the Frame Sync pattern used in Tx and Rx MSK data. Bit 7 of the MSB is compared to the
earliest received data. After a power on or C-BUS reset they are set to $CB23.
$C8 (P0.2-5) Scramble Seed 1 and 2
15
0
14
1
13
0
12
0
11
10
9
8
7
6
5
4
3
2
1
0
Bit:
P0.2
0
0
0
0
Scramble Seed 1 LSB
Scramble Seed 1 MSB
Scramble Seed 2 LSB
Scramble Seed 2 MSB
P0.3
P0.4
P0.5
0
0
0
1
1
1
0
0
0
0
0
0
These bits set the scramble seed used on all data bits following a Frame Head. If $0000 is programmed
as the seed then no scrambling will occur when selected. If either programmable scramble seeds are
selected, both the transmit and receive devices must use the same seed pattern for data to be
transferred correctly.
$C8 (P0.6-7) MSK Bit Sync
15
0
14
1
13
0
12
0
11
10
9
8
7
6
5
4
3
2
1
0
Bit:
P0.6
0
0
MSK Bit Sync LSB
MSK Bit Sync MSB
P0.7
0
1
0
0
This bit pattern is used when transmitting the bit sync portion of a Frame Head. After a power on or C-
BUS reset they are set to $5555 (‘0101…0101’).
2004 CML Microsystems Plc
52
D/882/7
CMLMICRO [ CML MICROCIRCUITS ]
