FRS Signalling Processor
CMX882
1.6.20.3 PROGRAMMING REGISTER Block 2 – CTCSS and DCS Setup:
$C8 (P2.0)
CTCSS and DCS TX LEVEL
Bit:
15
1
14
1
13
1
12
0
11
10
9
8
7
6
5
4
3
2
1
0
P2.0
CTCSS and DCS Level
Bits 11 (MSB) to 0 (LSB) set the transmitted CTCSS or DCS sub-audio signal level (pk-pk) with a
resolution of VDD(A)/16384 per LSB (0.183mV per LSB at VDD(A)=3V, giving a range 0 to 749.8mV pk-
pk).
$C8 (P2.1)
CTCSS TONE BW AND LEVEL
Bit:
15
0
14
1
13
1
12
0
11
10
0
9
8
7
6
5
4
3
2
1
0
DCS
CTCSS detect
P2.1
CTCSS and DCS detect threshold
24
bandwidth
Bit 11, DCS 24, sets the length of DCS code transmitted or searched for. When this bit is set to ‘1’ 24 bit
codes are transmitted and decoded. When this bit is set to ‘0’ 23 bit codes are used.
The ‘detect threshold’ bits (bits 9 to 4) set the minimum CTCSS or DCS signal level that will be detected.
The levels are set according to the formula:
Minimum Level = Detect Threshold × 2mV rms at VDD(A)
= 3V
The CTCSS detected tone bandwidth is set in accordance with the following table:
BANDWIDTH
Bit 3
Bit 2 Bit 1
Bit 0
Will Decode
Will Not Decode
Recommended for use with
split tones
0
0
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
±0.5%
±0.8%
±1.1%
±1.3%
±1.6%
±1.8%
±1.8%
±2.1%
±2.4%
±2.7%
±2.9%
±3.2%
Recommended for CTCSS ⇒
$C8 (P2.2-3) DCS CODE (LOWER) and DCS CODE (UPPER)
Bit:
15
0
14
1
13
1
12
0
11
10
9
8
7
6
5
4
3
2
1
0
P2.2
DCS Data (bits 11-0)
P2.3
0
1
1
0
DCS Data (bits 23/22-12)
These words set the DCS code to be transmitted or searched for. The least significant bit (bit 0) of the
DCS code is transmitted or compared first and the most significant bit is transmitted or compared last.
Note that DCS Data bit 23 is only used when bit 11 (DCS 24) of P2.1 is set to ‘1’.
$C8 (P2.4)
SUBAUDIO DROP OUT TIME
Bit:
15
0
14
1
13
1
12
0
11
10
9
8
7
6
5
4
3
2
1
0
P2.4
Subaudio Drop Out Time
0
The Subaudio Drop Out Time defines the time that the sub-audio signal detection can drop out before
loss of sub-audio is asserted. The period is set according to the formula:
Time = Subaudio Drop Out Time × 8.0ms
[range 0 to 120ms]
The setting of this register defines the maximum drop out time that the device can tolerate. The setting of
this register also determines the de-response time, which is typically 40ms longer than the programmed
drop out time.
2004 CML Microsystems Plc
54
D/882/7
CMLMICRO [ CML MICROCIRCUITS ]
