FRS Signalling Processor
CMX882
In Tx mode bit 7 will be set when the last bit of FFSK data has been transmitted. Note; when using type
0, 2 or 3 data formats (see section 1.5.5.4) this bit will only be set if bit 9 of the Modem Control register
($C7) is set at the appropriate time. After allowing a short time delay associated with the external
components and radio circuitry, the host may power down the CMX882 and transmitter or set the
CMX882 to transmit or receive new information as appropriate.
Bit 6 indicates that new transmit data is required (in Tx mode) or received data is ready to be read (in Rx
mode). For continuous transmission or reception of information, a data transfer should be completed
within the time appropriate for that data (see Table 9).
Bit 5 will be set after receiving the CRC portion of a sized Data Block (types 4 and 5) and will be set to ‘0’
when the locally calculated CRC indicates the received data has no errors.
Bits 4 and 3 indicate the received data rate after a valid data sequence has been received. If data Type
0 formatting is enabled these bits will be set on detection of a valid frame sync pattern. If Type 0
formatting is disabled then these bits will only be set when a Frame Head is detected with a correct CRC.
Rx 2400b/s
Rx1200b/s
Bit rate of detected valid data:
0
0
1
1
0
1
0
1
No data
1200b/s
2400b/s
Reserved
Programming Flag, bit 0: The Programming Register ($C8) should only be written to when bit 0 is set to
'1' (with both Mode select bits set low – See register $C8). Writing to the Programming Register ($C8)
clears bit 0 to '0'. Bit 0 is restored to '1' when the programming action is complete, normally within 250µs,
when it is then safe to write to the Programming Register.
1.6.18
Bit:
$C5 and $C9 RX DATA: 2 x 16-bit read-only
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Rx Data Byte 0
Rx Data Byte 1
$C5
$C9
(Frame Head: Address byte)
Rx Data Byte 2*
(Frame Head: Format byte)
Rx Data Byte 3*
(Frame Head: Size / Information byte)
(Frame Head: CRC byte)
XTCSS Tone 3 (S1)
XTCSS Tone 2 (S0)
XTCSS received address
*$C9 is used when receiving Type 4 and 5 formats and Frame Heads, the Rx buffer is effectively 4 bytes long in these cases.
These 2 words hold the most recent 2 bytes (Byte 0 and 1) or 4 bytes (Bytes 0, 1, 2 and 3) of MSK data
decoded. Received data is continuous, if the data is not read before the next data is received the current
data will be over-written.
$C9 holds the information decoded after receiving an XTCSS type tone set. Bits 7 to 0 represent the
received address in hex based on the XTCSS tones A1 and A0. This register will only be updated if the
received address matches the one programmed in the Audio and Device Address Control register or is
the all call address of '40'. Bits 15 to 12 and 11 to 8 defines the received S1 and S0 tones, see Table 6
and section 1.5.6.
Although $C9 holds both Rx data and Rx XTCSS tone information, only one type of signal will be present
in the received signal at any one time so no conflict will occur.
After receiving a Frame Head the host can read the Address and Size / Information bytes for the
following packet from $C5 and optionally the Control byte and the Frame Head Checksum A byte from
$C9. The CMX882 will read the Size and Message formatting information and if the message is of type
3, 4 or 5 (see section 1.5.5.4) it will set the automatic decoding of the following data; descrambling, de-
interleaving, decoding error correction bytes, stripping out pad bytes, calculating and checking Checksum
2004 CML Microsystems Plc
48
D/882/7
CMLMICRO [ CML MICROCIRCUITS ]
