FRS Signalling Processor
CMX882
1.6.20.4 PROGRAMMING REGISTER Block 3 – Reserved
1.6.20.5 PROGRAMMING REGISTER Block 4 – Gain and Offset Setup
$C8 (P4.0)
FINE INPUT GAIN
Bit:
15
1
14
0
13
12
11
10
9
8
7
6
5
4
3
2
1
0
P4.0
Fine Input Gain (unsigned integer)
Gain = 20 × log([32768-IG]/32768) IG is the unsigned integer value in the ‘Fine Input Gain’ field
Fine input gain adjustment should be kept within the range 0 to -3.5dB.
$C8 (P4.1)
Reserved
Bit:
15
0
14
0
13
12
11
10
9
8
7
6
5
4
3
3
2
2
1
1
0
0
P4.1
Reserved - set to '0'
This register is reserved and should be set to '0'.
$C8 (P4.2-3) FINE OUTPUT GAIN 1 and FINE OUTPUT GAIN 2
Bit:
P4.2
P4.3
15
0
14
0
13
12
11
10
9
8
7
6
5
4
Fine Output Gain 1 (unsigned integer)
0
0
Fine Output Gain 2 (unsigned integer)
Gain = 20 × log([32768-OG]/32768) OG is the unsigned integer value in the ‘Fine Output Gain’ field
Fine output gain adjustment should be kept within the range 0dB to -3.5dB.
$C8 (P4.4-5) OUTPUT 1 OFFSET and OUTPUT 2 OFFSET
Bit:
P4.4
P4.5
15
0
14
0
13
12
11
10
9
8
7
6
5
4
3
2
1
0
2’s complement offset for MOD_1, resolution = V (A)/16384 per LSB
DD
0
0
2’s complement offset for MOD_2, resolution = V (A)/16384 per LSB
DD
Can be used to compensate for inherent offsets in the output path via MOD_1 (Output 1 Offset) and
MOD_2 (Output 2 Offset). It is recommended that the offset correction is kept within the range +/-50mV.
$C8 (P4.6)
RAMP RATE CONTROL
Bit:
15
0
14
0
13
12
11
10
9
8
7
6
5
4
3
2
1
0
P4.6
Ramp Rate Up Control (RRU)
Ramp Rate Down control (RRD)
The ramp-up and ramp-down rates can be independently programmed. The ramp rates apply to all the
analogue output ports. They only affect those ports being turned on (ramp-up) or turned off (ramp down).
The ramp rates should be programmed before ramping any outputs.
Time to ramp-up to full gain =
(1 + RRU) × 1.333ms
(1 + RRD) × 1.333ms
Time to ramp down to zero gain =
2004 CML Microsystems Plc
55
D/882/7
CMLMICRO [ CML MICROCIRCUITS ]
