TETRA Baseband Processor
FX980
1.5.3
Rx Data Path
1.5.3.1 Anti-Alias Filtering and Sigma-Delta A-D Converters
The sampling frequency of the Sigma-Delta A-D is 128x symbol rate. The high oversampling rate
relaxes the design requirements on the anti-alias filter. However, to achieve optimum performance the
anti-alias filter must reject the sampling frequency to about -110dB, of which at least 40dB must be
provided externally. Additionally, in order to ease the complexity of the subsequent digital filters, there
is a further requirement that the anti-alias filter suppress 8x symbol rate to about -30dB. The on-chip
anti-alias filter is designed to achieve this when used in conjunction with some external filtering. If
required, the on-chip anti-alias filter can be by-passed and powered down, although external anti-
aliasing must then be provided. The 4th order Sigma-Delta A-D converters are designed to have low
distortion and >96dB dynamic range. The baseband I and Q channels must be provided as differential
signals; this minimises in-band pick up both on and off the chip.
1.5.3.2 Filters
Digital filtering is applied to the data from the Sigma-Delta A-D converters; the default coefficients are
set to give a Root Raised Cosine response with roll-off factor of 0.35. These FIR filters are configured,
for each channel, as three filters in cascade. The first filter gives sufficient rejection at 8x symbol rate
to permit decimation at that frequency (note that -30dB is provided by the primary anti-alias filters).
The second filter has 63 taps and is used to enhance stop-band rejection. The third filter has 49 taps
and provides the primary shaping requirements. Coefficients for the second and third filters are
programmable via the serial interface. This gives the opportunity, if required, to fine tune the
frequency response of a complete system so as to minimise the BER or to use the device in other
applications. The filters can also be by-passed if required, by setting the centre coefficient to maximum
and all other coefficients to zero.
1.5.3.3 Offset Registers
System generated offsets may be removed by control of the offset register via the serial interface.
1.5.3.4 I and Q Channel Gain
Programmable gain modules are provided in both I and Q channels. These blocks allow the user to
adjust the dynamic range of the received data within the digital filters, thus optimising the filter signal
to noise performance for a range of levels at the Rx input pins.
The two channels are independently programmable. This enables differential gain corrections to be
made within the digital domain.
1.5.4
Auxiliary Circuits
1.5.4.1 10-Bit DACs
Four 10-bit DACs are provided to assist in a variety of control functions. The DACs are designed to
provide an output as a proportion of the supply voltage, depending on the digital input. They are
monotonic with an absolute accuracy of better than 1%. Control and Data for these come via the serial
interface.
1.5.4.2 10-Bit ADC
A 10-bit ADC is provided to assist in a variety of measurement and control functions. The ADC is
designed to produce a digital output proportional to the input voltage; full scale being the positive
supply. It is monotonic with an absolute accuracy of about 1%. An input multiplexer allows the input to
be selected from one of four sources. Control and digital data output is via the serial interface.
©
1997
Consumer Microcircuits Limited
9
D/980/3
CMLMICRO [ CML MICROCIRCUITS ]
