TETRA Baseband Processor
FX980
Two control bits are associated with each data transmission word. One controls the format of the word
and the other initiates and terminates a transmission cycle. This close association enables precise
control of the transmission frame. To relieve the user of the need to synchronise each TxData write
with the internal transmit cycle, transmit data words are written into an internal 4-word-deep FIFO.
Symbols or constellation points are then read as needed from this FIFO. It is necessary to make sure
that there is always a word to be read, and also that the FIFO is never written to when full. This may
be accomplished by using one of two data interlock mechanisms.
Data Interlock Mechanisms
There are two possible transmission data interlock mechanisms. It is recommended that the user
should always use one of these methods.
·
·
Software polling.
Serial Clock when ready.
Software polling requires the user to first check that the FIFO is not full before writing each TxData
word. This may be accomplished by inspecting the relevant FIFO status bits before writing one or
more TxData words.
The Serial Clock when ready method is a hardware interlock mechanism (enabled by setting the
TxHandshakeEn bit of ConfigCtrl1 register active). The mechanism allows the user to write TxData
words without doing any FIFO checks: the hardware handshake is implemented by stopping the serial
port clock when the FIFO is full. To prevent a serial port lockout-condition, the handshake is only
enabled once the transmission frame has been initiated and is automatically disabled at the end of a
frame. This mechanism should be used with care, because stopping the clock will freeze all other
serial port transfers (the serial port clock SClk is common to all three serial ports), including access to
auxiliary data converters and receive data.
Power Ramping and Frame Interlock
The RampUp bit in the TxData word is used to control both the power ramping function and the frame
activation. To start a transmission frame, a transmission word is written with the RampUp bit active. All
subsequent TxData words prior to frame termination must also have this bit active. The frame is
terminated by writing transmit data words with the RampUp bit inactive. Subsequent TxData words
must also have this bit inactive, until initiation of a new frame is required. While the power ramping is
active (up or down) the user must supply transmission symbols or valid constellation points. Once the
ramp down operation has completed, all subsequent TxData writes with the RampUp bit inactive will
be ignored.
1.5.6.5 Command Control Serial Word
A command word either directly accesses an internal register for a read or write operation, or
addresses a memory access point to indirectly access a block of internal memory. For test purposes
all registers that can be written may also be read. Not all registers may be written, as some are just
status registers. Each register or memory access point is assigned a unique address: the whole (8-
bit) address range is reserved for the FX980.
Indirect Memory Addressing
All internal memory access is via an access point. First, a command word access is used to reset the
internal address pointer, then data port access operations post-increment this address pointer.
ã 1997 Consumer Microcircuits Limited
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D/980/3
CMLMICRO [ CML MICROCIRCUITS ]
