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FX029D5 参数 Datasheet PDF下载

FX029D5图片预览
型号: FX029D5
PDF下载: 下载PDF文件 查看货源
内容描述: [Audio Amplifier, 2 Channel(s), 1 Func, CMOS, PDSO24, SSOP-24]
分类和应用: 放大器光电二极管商用集成电路
文件页数/大小: 7 页 / 108 K
品牌: CMLMICRO [ CML MICROCIRCUITS ]
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Specification  
Absolute Maximum Ratings  
Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits  
is not implied.  
Supply voltage  
-0.3 to 7.0V  
Input voltage at any pin (ref. VSS = 0V)  
-0.3 to (VDD + 0.3V)  
Sink/source current (supply pins)  
(other pins)  
+/- 30mA  
+/- 20mA  
Total device dissipation (DW/J) @ TAMB 25°C  
(D5) @ TAMB 25°C  
800mW Max.  
550mW Max.  
Derating  
(DW/J)  
(D5)  
10mW/°C  
9mW/°C  
Operating temperature range: FX029DW/D5/J  
-40°C to +85°C  
Storage temperature range:  
FX029D5  
FX029DW/J  
-40°C to +85°C  
-55°C to +125°C  
Operating Characteristics  
All device characteristics are measured under the following conditions unless otherwise specified:  
VDD = 5.0V, TAMB = 25°C. External components as Figure 2. Audio 0dB ref. = 775mVrms  
Characteristics  
Supply Voltage  
See Note  
Min.  
4.5  
Typ.  
5.0  
Max.  
5.5  
Unit  
V
Current  
(All Stages Mute)  
(All Stages Operating)  
-
-
0.10  
3.0  
-
-
mA  
mA  
Digital Inputs  
4
Input Logic “1”  
Input Logic “0”  
Digital Input Impedances  
3.5  
-
0.5  
-
-
-
1.5  
-
V
V
MΩ  
1.0  
Gain Control Amplifier Stages (Stages 1 and 2)  
Bandwidth (-3dB)  
1
3.3  
-
-
-
46.0  
46.0  
-
-
50.0  
-
-
-
kHz  
kΩ  
%
dB  
dB  
dB  
dB/step  
dB  
Output Impedance  
1.0  
0.35  
60.0  
48.0  
48.0  
2.0  
-
2.0  
0.5  
-
-
Total Harmonic Distortion  
Interstage Isolation  
Gain  
2, 5  
Attenuation  
Gain/Attenuation Step Size  
Step Error  
-
-
0.4  
-
Input Impedance  
-
kΩ  
mV  
Input Referred Offset Voltage (VIOS  
Uncommitted Amplifier (Stage 3)  
Bandwidth (-3dB)  
)
10.0  
-
3
3
10.0  
-
-
kHz  
kΩ  
%
Output Impedance  
-
-
-
1.0  
0.35  
60  
2.0  
0.5  
-
Total Harmonic Distortion  
Open Loop DC Gain  
Timing (See Figure 3)  
dB  
Serial Clock “High” Pulse Width (tPWH  
)
250  
250  
150  
50.0  
200  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
MHz  
Serial Clock “Low” Pulse Width (tPWL  
Data Set-up Time (tDS)  
)
Data Hold Time (tDH)  
Load/Latch Delay (tLLD  
Load/Latch Over-Time (tLLO  
Load/Latch Pulse Width (tLLW  
Serial Data Clock Frequency  
)
)
0
-
2.0  
)
150  
-
Notes  
1. Gain set to maximum (+48.0dB).  
2. Gain Set 0dB. Input Level 1.0kHz, -3.0dB (549mVrms).  
3. Gain externally set to 10.0dB.  
4. Serial Clock, Serial Data and Load/Latch inputs.  
5. With a 100kload on the relevant output.  
5
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