Application Information
External Components
VDD
C7
VDD
SERIAL CLOCK
SERIAL DATA
LOAD/LATCH
VSS
16
15
14
13
12
11
1
2
IN 3
OUT 3
3
OUT 1A
OUT 1B
OUT 2
IN 1C
C1
C2
C3
C4
IN 1A
IN 1B
IN 2A
IN 2B
4
5
FX029
DW/J
6
C5
10
9
7
8
VBIAS
VSS
VSS
Fig.2 Recommended External Components
Component Recommendations
Application Recommendations
Component
Value
0.1µF
To avoid noise and instability the following practices
are recommended:
C1
C2
C3
0.1µF
0.1µF
(a) Use a clean, well-regulated power supply.
(b) Keep tracks short.
C4
C5
0.1µF
0.1µF
(c) Inputs and outputs should be shielded wherever
possible.
C6
C7
Not Used
1.0µF
(d) Analogue tracks should not run parallel to digital
tracks.
Tolerances 20%
(e) A “Ground Plane” connected to VSSwill assist in
eliminating external pick-up on the channel input
and output pins.
(f) Avoid running high level outputs adjacent to low
level inputs.
(g) The serial clock should not be running
consecutively when not in the process of actually
loading data.
Input capacitors C1 to C5 are only required for ac
input signals; dc input signals do not require these
components.
The gain of the uncommitted stage (3) is set by
external components employed around the input and
output pins (see Specification page).
Serial Interface Timing
t PWH
SERIAL
CLOCK
t PWL
14TH
CLOCK
PULSE
1ST
CLOCK
PULSE
SERIAL
DATA
t DS
t DH
D0
D13
D1
D12
tLLD
tLLO
LOAD/LATCH
tLLW
Fig.3 Serial Timing Diagram - see Specification page for timing specifications
3
CMLMICRO [ CML MICROCIRCUITS ]
