Control Data and Timing
The gain and I/O signal path for each section (Channels 1 and 2) is set individually by a 14-bit data word (D0 to
D13). Data is loaded on the rising edge of the Serial Clock. Loaded data is executed on the rising edge of the Load/
Latch pulse.The 14-bit word consists of 1 channel address bit (D7) for selection of the channel to be programmed,
6 bits for setting the amplification/attenuation level (D8-D13), 3 bits for input selection (D4 and D6), and 4 bits for
output settings (D0-D3). This format is illustrated below in Figure 4.
Tables 1-3 show how the data word is used to control channel selection, amplification/attenuation, input selection
and output settings, respectively.
D9
D13 D12 D12 D10
D7
D6
D5
D4
D3
D2
D1
D0
D8
GAIN/ATTENUATION
LEVEL
INPUT
SELECT
OUTPUT
SETTINGS
CHANNEL
ADDRESS
Fig.4 Level-Controlling Data Word Format
D13 D12 D11 D10 D9 D8
Gain
Set (dB)
D13 D12 D11 D10 D9 D8
Gain
Set (dB)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
MUTE
-48
-46
-44
-42
-40
-38
-36
-34
-32
-30
-28
-26
-24
-22
-20
-18
-16
-14
-12
-10
-8
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
48
48
-6
-4
-2
0
Table 1 - Amplification/Attenuation Level
D7
Stage
Selected
D6 D5 D4
Inputs
Selected
D3 D2
Output
1B
D1 D0
Outputs
1A & 2
0
1
1
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
none
1
2
0
0
1
1
0
1
0
1
high Z
enabled
VSS
0
0
1
1
0
1
0
1
high Z
enabled
VSS
1 and 2
VBIAS
VBIAS
3
Table 3 Stage Output Selection
1 and 3
2 and 3
1, 2 and 3
Table 2 Stage and Input Selection
4
CMLMICRO [ CML MICROCIRCUITS ]
