Marine VHF Audio and Signalling Processor
CMX885
8.1.7 SYSCLK1 and SYSCLK2 PLL Data – $AB, $AD write
C-BUS address: $AB – SYSCLK1 PLL
C-BUS address: $AD – SYSCLK2 PLL
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VCO Op Divide Ratio <5-0>
PLL Feedback Divide Ratio <9-0>
b15-10
b9-0
divide the selected output clock source by the value in these bits, to generate the System
Clock output. Divide by 64 is selected by setting these bits to 0.
divide System Clock PLL VCO clock by value set in these bits as feedback to the PLL
phase detector (PD); when the PLL is stable, this will be the same frequency as the
internal reference as set by b8-b0 of the System Clock Reference and Source
Configuration register ($AC). Divide by 1024 is selected by setting these bits to 0.
8.1.8 SYSCLK1 and SYSCLK2 REF – $AC and $AE write
C-BUS address: $AC – SYSCLK1 Ref
C-BUS address: $AE – SYSCLK2 Ref
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Select & PS Clock Sources
O/P Slew
Ref Clock Divide Ratio <8-0>
b15,12,11Clock output divider source
SYSCLK1 Source
Xtal
SYSCLK1 PLL
Main PLL
Test
b15
b12
x
0
0
1
b11
x
0
1
x
0
1
1
1
SYSCLK2 Source
Xtal
b15
0
b12
x
b11
x
SYSCKL2 PLL
Main PLL
1
1
0
0
0
1
SYSCLK1 PLL
Test
1
1
1
1
0
1
b14
Powersave PLL
0 = powersave
1 = enabled
b13
b10-9
Powersave Output Divider
Output Slew Rate
0 = powersave / bypass 1 = enabled
b10 b9
Output Slew Rate
0
0
1
1
0
1
0
1
normal
slow
fast
fast
b8-b0
Reference Clk divide value. Divide by 512 function is selected by setting these bits to 0.
Note that after a General Reset, there will be no signal present on the SYSCLK1 and SYSCLK2 pins.
© 2010 CML Microsystems Plc
39
D/885/3
CMLMICRO [ CML MICROCIRCUITS ]
