Programmable Paging Tone Decoder
CMX823
These four bits set the nominal bandwidth of the tone
decoder according to the table below:
DECODER
BANDWIDTH
(Bits 5, 4, 3 and 2)
BANDWIDTH
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Nominal Decode
±0.1%
0
0
0
1
±0.3%
0
0
1
0
±0.5%
0
0
1
1
±0.7%
0
1
0
0
±0.9%
0
1
0
1
±1.1%
0
1
1
0
±1.3%
0
1
1
1
±1.5%
1
0
0
0
±1.7%
1
0
0
1
±1.9%
1
0
1
0
±2.1%
1
0
1
1
±2.3%
1
1
0
0
±2.5%
1
1
0
1
±2.7%
1
1
1
0
±2.9%
1
1
1
1
±3.1%
These two bits select the mode of operation of the device.
OPERATION MODE
(Bits 1 and 0)
Bit 1
Bit 0
OPERATION MODE
0
0
0
1
Zero-Power state.
CLEAR RAM: Clears all of the contents of the selected RAM. The RAM
FULL bit of the STATUS Register is reset to 0. Wait 100ns after setting
this mode, so that the clear operation can complete.
Normal operation, tone decoding enabled.
1
1
0
1
Reserved for future use.
AUXILIARY CONTROL Register (Hex address $32)
Reserved for future use. These bits should be reset to "0".
(Bit 7 to Bit 1)
(Bit 0)
This bit controls the input signal flow. In normal use it should be set to “0”, but
during the loading of RAM values it should be set to “1”, to prevent a spurious
input from disrupting the loading process.
ã 2003 CML Microsystems Plc
10
D/823/3
CMLMICRO [ CML MICROCIRCUITS ]
